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1. 发明授权

US07205811B2 Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias 有权
标题翻译：使用可调偏置在相位内插器中保持时钟边缘期望斜率的方法和装置
公开(公告)号：US07205811B2
公开(公告)日：2007-04-17
申请号：US11095772
申请日：2005-03-31
申请人： Ronald L. Freyman , Craig B. Ziemer
发明人： Ronald L. Freyman , Craig B. Ziemer
IPC分类号： H03K5/13
CPC分类号： H03K6/04
摘要： Methods and apparatus are provided for maintaining a desired slope of clock edges in a phase interpolator using an adjustable bias. The disclosed phase interpolator comprises at least one delay element to generate at least two interpolation signals each having an associated phase and a variable slope unit associated with each of the at least two interpolation signals, wherein a slope of each of the variable slope units is controlled by a bias signal and is varied based on a data rate of the interpolation signals. The slope is varied to maintain a desired slope of clock edges associated with the interpolation signals. The slope can be maintained, for example, between approximately the value of the delay between consecutive clock edges and twice the value of the delay between consecutive clock edges.
摘要翻译：提供的方法和装置用于使用可调偏置来保持相位插值器中的时钟边缘的期望斜率。所公开的相位插值器包括至少一个延迟元件，以产生每个具有相关联的相关联的至少两个插值信号和与至少两个内插信号中的每一个相关联的可变斜率单元，其中每个可变斜率单元的斜率被控制通过偏置信号，并且基于插值信号的数据速率而变化。改变斜率以保持与内插信号相关联的时钟边缘的期望斜率。斜率可以维持在例如在连续时钟边缘之间的延迟的近似值和连续时钟边缘之间的延迟值的两倍之间。

2. 发明授权

US07190198B2 Voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟回路
公开(公告)号：US07190198B2
公开(公告)日：2007-03-13
申请号：US10999889
申请日：2004-11-30
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03L7/06
CPC分类号： G06F1/04
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟回路包括至少一个延迟元件以产生参考时钟的至少两个相位; 中央内插器，用于内插参考时钟的至少两个相位以产生内插信号; 以及将内插信号注入延迟级的输入。中央插值器提供精细的相位控制。此外，可以通过选择性地将内插信号注入到给定的延迟级中来可选地实现粗略的相位控制。公开了使用多个内插器的粗略和精细相位控制的另一个电压控制延迟回路。

3. 发明授权

US07928789B2 Methods and apparatus for improved phase switching and linearity in an analog phase interpolator 有权
标题翻译：用于改善模拟相位内插器中的相位切换和线性度的方法和装置
公开(公告)号：US07928789B2
公开(公告)日：2011-04-19
申请号：US12344047
申请日：2008-12-24
申请人： Ronald L. Freyman , Craig B. Ziemer
发明人： Ronald L. Freyman , Craig B. Ziemer
IPC分类号： H03K11/16
CPC分类号： H03C3/225
摘要： Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.
摘要翻译：提供了用于改善模拟相位内插器中的相位切换和线性度的方法和装置。根据本发明的相位插值器包括（i）多个尾电流源，其在相位内插器可操作时基本上被激活; （ii）至少两对输入晶体管器件，其中一对输入晶体管器件与相位内插器的最小相位相关联，另一对输入晶体管器件与相位内插器的最大相位相关联; 以及（iii）多个电流转向开关，其基于所施加的内插控制信号，将多个尾电流源产生的电流提供给所述至少两对输入晶体管器件中的一个或多个。

4. 发明申请

US20090108898A1 METHODS AND APPARATUS FOR IMPROVED PHASE SWITCHING AND LINEARITY IN AN ANALOG PHASE INTERPOLATOR 有权
标题翻译：改进的相位切换和模拟相位插值器的线性度的方法和装置
公开(公告)号：US20090108898A1
公开(公告)日：2009-04-30
申请号：US12344047
申请日：2008-12-24
申请人： Ronald L. Freyman , Craig B. Ziemer
发明人： Ronald L. Freyman , Craig B. Ziemer
IPC分类号： H03H11/16
CPC分类号： H03C3/225
摘要： Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.
摘要翻译：提供了用于改善模拟相位内插器中的相位切换和线性度的方法和装置。根据本发明的相位插值器包括（i）多个尾电流源，其在相位内插器可操作时基本上被激活; （ii）至少两对输入晶体管器件，其中一对输入晶体管器件与相位内插器的最小相位相关联，另一对输入晶体管器件与相位插值器的最大相位相关联; 以及（iii）多个电流转向开关，其基于所施加的内插控制信号，将多个尾电流源产生的电流提供给所述至少两对输入晶体管器件中的一个或多个。

5. 发明授权

US07298195B2 Methods and apparatus for improved phase switching and linearity in an analog phase interpolator 失效
标题翻译：用于改善模拟相位内插器中的相位切换和线性度的方法和装置
公开(公告)号：US07298195B2
公开(公告)日：2007-11-20
申请号：US11095771
申请日：2005-03-31
申请人： Ronald L. Freyman , Craig B. Ziemer
发明人： Ronald L. Freyman , Craig B. Ziemer
IPC分类号： H03K5/13
CPC分类号： H03C3/225
摘要： Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.
摘要翻译：提供了用于改善模拟相位内插器中的相位切换和线性度的方法和装置。根据本发明的相位插值器包括（i）多个尾电流源，其在相位内插器可操作时基本上被激活; （ii）至少两对输入晶体管器件，其中一对输入晶体管器件与相位内插器的最小相位相关联，另一对输入晶体管器件与相位内插器的最大相位相关联; 以及（iii）多个电流转向开关，其基于所施加的内插控制信号，将多个尾电流源产生的电流提供给所述至少两对输入晶体管器件中的一个或多个。

6. 发明授权

US07560967B2 Methods and apparatus for improved phase switching and linearity in an analog phase interpolator 失效
标题翻译：用于改善模拟相位内插器中的相位切换和线性度的方法和装置
公开(公告)号：US07560967B2
公开(公告)日：2009-07-14
申请号：US11870204
申请日：2007-10-10
申请人： Ronald L. Freyman , Craig B. Ziemer
发明人： Ronald L. Freyman , Craig B. Ziemer
IPC分类号： H03K11/16
CPC分类号： H03C3/225
摘要： Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.
摘要翻译：提供了用于改善模拟相位内插器中的相位切换和线性度的方法和装置。根据本发明的相位插值器包括（i）多个尾电流源，其在相位内插器可操作时基本上被激活; （ii）至少两对输入晶体管器件，其中一对输入晶体管器件与相位内插器的最小相位相关联，另一对输入晶体管器件与相位内插器的最大相位相关联; 以及（iii）多个电流转向开关，其基于所施加的内插控制信号，将多个尾电流源产生的电流提供给所述至少两对输入晶体管器件中的一个或多个。

7. 发明授权

US07236037B2 Alternating clock signal generation for delay loops 失效
标题翻译：用于延迟环的交替时钟信号生成
公开(公告)号：US07236037B2
公开(公告)日：2007-06-26
申请号：US11138777
申请日：2005-05-26
申请人： Christopher J. Abel , Vladimir Sindalovsky , Craig B. Ziemer
发明人： Christopher J. Abel , Vladimir Sindalovsky , Craig B. Ziemer
IPC分类号： H03K3/00
CPC分类号： H04L7/0025 , H03L7/07 , H03L7/0814 , H04L7/0337
摘要： A delay loop (e.g., a voltage-controlled delay loop) has (at least) two devices (e.g., interpolators) for generating clock signals for injection into the delay elements of the delay loop in a leap-frog manner, in which, while one interpolator is generating the clock signal currently selected for injection, the other interpolator can be controlled to generate the next clock signal to be selected for injection. This leap-frog technique can provide more settling time for generating injected clock signals than implementations that rely on a single interpolator.
摘要翻译：延迟环路（例如，电压控制延迟环路）具有（至少）两个用于产生用于以跳跃方式注入到延迟环路的延迟元件中的时钟信号的器件（例如，内插器），其中，一个内插器正在产生当前被选择用于注入的时钟信号，另一个内插器可被控制以产生要被选择用于注入的下一个时钟信号。这种跳跃式技术可以提供更多的建立时间来产生注入的时钟信号，而不是依赖于单个内插器的实现。

8. 发明授权

US06381086B1 Programmable active damping for high-speed write driver 有权
标题翻译：高速写入驱动器的可编程有源阻尼
公开(公告)号：US06381086B1
公开(公告)日：2002-04-30
申请号：US09607337
申请日：2000-10-23
申请人： Reed H. Koenig , Craig B. Ziemer
发明人： Reed H. Koenig , Craig B. Ziemer
IPC分类号： G11B502
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B2005/0013
摘要： Programmable active damping of the overshoot in the bipolar write driver output current waveform in the write head of a hard disk drive is provided by subtracting, a controlled amount of current from the writer current, for a predetermined duration, at the beginning of each transition of the write driver output current.
摘要翻译：在硬盘驱动器的写入头中的双极性写入驱动器输出电流波形中的过冲的可编程有源阻尼是通过从每个转换开始时从写入器电流中减去一个受控量的电流达预定的持续时间写驱动器输出电流。

9. 发明授权

US07787515B2 Method and apparatus for generation of asynchronous clock for spread spectrum transmission 有权
标题翻译：用于产生扩频传输的异步时钟的方法和装置
公开(公告)号：US07787515B2
公开(公告)日：2010-08-31
申请号：US11353431
申请日：2006-02-14
申请人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , William B. Wilson , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , William B. Wilson , Craig B. Ziemer
IPC分类号： H04B1/00
CPC分类号： H04L27/0014 , H04B1/7075 , H04L2027/0036
摘要： A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.
摘要翻译：用于扩频率控制的电路使用第一内插器在第一信号和第二信号之间进行相位插值，并且基于第一控制信号产生第一输出信号。第二内插器用于在第三信号和第四信号之间进行相位插值，并且基于第二控制信号产生第二输出信号。多路复用器用于基于选择信号选择第一输出信号或第二输出信号作为扩频时钟（SSCLK）。跳跃内插器控制用于与SSCLK同步地产生基于第一类型的相位调整请求的第一控制信号，基于第二类型的相位调整请求的第二控制信号，以及选择信号在改变第一控制信号或第二控制信号之后允许内插器稳定时间之后，在第一输出信号和第二输出信号之间切换多路复用器。

10. 发明申请

US20080001644A1 Phase interpolator with output amplitude correction 有权
公开(公告)号：US20080001644A1
公开(公告)日：2008-01-03
申请号：US11479749
申请日：2006-06-30
申请人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
发明人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , H03K2005/00052 , H03K2005/00156 , H03K2005/00195
摘要： A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

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