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1. 发明授权

US08816753B2 Trim circuit for power supply controller 有权
标题翻译：电源控制器微调电路
公开(公告)号：US08816753B2
公开(公告)日：2014-08-26
申请号：US13073862
申请日：2011-03-28
申请人： Rui-Hong Lu , Han-Chung Tai , Hsin-Chih Chiang
发明人： Rui-Hong Lu , Han-Chung Tai , Hsin-Chih Chiang
IPC分类号： H01H37/76 , G11C17/18
CPC分类号： G11C17/18 , G11C17/16
摘要： A trim circuit for a power supply controller includes: a control circuit; at least a capacitance type programmable circuit connection; and a switching circuit, under control of the control circuit, the switching circuit selectively coupling the capacitance type programmable circuit connection to anyone of an operation voltage and a programming voltage, for determining a programming state of the capacitance type programmable circuit connection.
摘要翻译：电源控制器的微调电路包括：控制电路; 至少电容式可编程电路连接; 以及开关电路，在所述控制电路的控制下，所述开关电路将所述电容式可编程电路连接选择性地耦合到任何操作电压和编程电压，以确定所述电容型可编程电路连接的编程状态。

2. 发明申请

US20120249220A1 Trim Circuit for Power Supply Controller 有权
标题翻译：电源控制器微调电路
公开(公告)号：US20120249220A1
公开(公告)日：2012-10-04
申请号：US13073862
申请日：2011-03-28
申请人： Rui-Hong Lu , Han-Chung Tai , Hsin-Chih Chiang
发明人： Rui-Hong Lu , Han-Chung Tai , Hsin-Chih Chiang
IPC分类号： H01H37/74
CPC分类号： G11C17/18 , G11C17/16
摘要： A trim circuit for a power supply controller includes: a control circuit; at least a capacitance type programmable circuit connection; and a switching circuit, under control of the control circuit, the switching circuit selectively coupling the capacitance type programmable circuit connection to anyone of an operation voltage and a programming voltage, for determining a programming state of the capacitance type programmable circuit connection.
摘要翻译：电源控制器的微调电路包括：控制电路; 至少电容式可编程电路连接; 以及开关电路，在所述控制电路的控制下，所述开关电路将所述电容式可编程电路连接选择性地耦合到任何操作电压和编程电压，以确定所述电容型可编程电路连接的编程状态。

3. 发明授权

US09184097B2 Semiconductor devices and formation methods thereof 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US09184097B2
公开(公告)日：2015-11-10
申请号：US12574793
申请日：2009-10-07
申请人： Hsin-Chih Chiang , Han-Chung Tai
发明人： Hsin-Chih Chiang , Han-Chung Tai
IPC分类号： H01L21/82 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823892 , H01L21/82385 , H01L21/823857 , H01L27/0928
摘要： A semiconductor device is provided and includes a substrate of a first conductivity type, a deep well of a second conductivity type, and a first high-side device. The deep well is formed on the substrate. The first high-side device is disposed within the deep well and includes an insulation layer of the second conductivity type, a well of the first conductivity type, first and second regions of the second conductivity type, and a first poly-silicon material. The insulation layer is formed on the substrate. The well is formed within the deep well. The first and second regions are formed within the well. The first poly-silicon material is disposed between the first region and the second region and on the deep well.
摘要翻译：提供了半导体器件，并且包括第一导电类型的衬底，第二导电类型的阱和第一高侧器件。在衬底上形成深井。第一高侧装置设置在深井内，并且包括第二导电类型的绝缘层，第一导电类型的阱，第二导电类型的第一和第二区域以及第一多晶硅材料。绝缘层形成在基板上。井在深井内形成。第一和第二区域形成在井内。第一多晶硅材料设置在第一区域和第二区域之间以及深井之间。

4. 发明申请

US20110180858A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20110180858A1
公开(公告)日：2011-07-28
申请号：US12828366
申请日：2010-07-01
申请人： Hsin-Chih Chiang , Han-Chung Tai
发明人： Hsin-Chih Chiang , Han-Chung Tai
IPC分类号： H01L27/085
CPC分类号： H01L27/085 , H01L29/7803 , H01L29/8083
摘要： A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. Wherein the first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second drain electrode of the JFET respectively.
摘要翻译：半导体器件。半导体包括衬底，VDMOS，JFET，第一电极，第二电极，第三电极和第四电极。 VDMOS形成在基板中。 JFET形成在衬底中。其中，第一电极，第二电极和第三电极分别连接到VDMOS并用作VDMOS的第一栅电极，第一漏电极和第一源电极。第二电极，第三电极和第四电极分别连接到JFET并用作JFET的第二漏电极，第二栅电极和第二漏电极。

5. 发明申请

US20110180878A1 High Side Semiconductor Structure 有权
标题翻译：高边半导体结构
公开(公告)号：US20110180878A1
公开(公告)日：2011-07-28
申请号：US12832727
申请日：2010-07-08
申请人： Han-Chung Tai , Hsin-Chih Chiang
发明人： Han-Chung Tai , Hsin-Chih Chiang
IPC分类号： H01L27/092 , H01L27/088
CPC分类号： H01L21/823892 , H01L27/088 , H01L27/0928 , H01L29/1083
摘要： A high side semiconductor structure is provided. The high side semiconductor structure includes a substrate, a first deep well, a second deep well, a first active element, a second active element and a doped well. The first deep well and the second deep well are formed in the substrate, wherein the first deep well and the second deep well have identical type of ion doping. The first active element and the second active element are respectively formed in the first deep well and the second deep well. The doped well is formed in the substrate and is disposed between the first deep well and the second deep well. The doped well, the first deep well and the second deep well are interspaced, and the type of ion doping of the first deep well and the second deep well is complementary with that of the doped well.
摘要翻译：提供了高边半导体结构。高侧半导体结构包括衬底，第一深阱，第二深阱，第一有源元件，第二有源元件和掺杂阱。在衬底中形成第一深阱和第二深阱，其中第一深阱和第二深阱具有相同类型的离子掺杂。第一有源元件和第二有源元件分别形成在第一深阱和第二深阱中。掺杂阱形成在衬底中并且设置在第一深阱和第二深阱之间。掺杂阱，第一深阱和第二深阱是间隔的，第一深阱和第二深阱的离子掺杂类型与掺杂阱的离子掺杂类型互补。

6. 发明授权

US08373253B2 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US08373253B2
公开(公告)日：2013-02-12
申请号：US12875455
申请日：2010-09-03
申请人： Han-Chung Tai , Hsin-Chih Chiang
发明人： Han-Chung Tai , Hsin-Chih Chiang
IPC分类号： H01L29/861
CPC分类号： H01L27/0727 , H01L27/0255 , H01L27/0259
摘要： A semiconductor structure. The semiconductor comprises a substrate, a first deep well, a diode and a transistor. The first deep well is formed in the substrate. The diode is formed in the first deep well. The transistor is formed in the first deep well. The diode is connected to a first voltage, the transistor is connected to a second voltage, and the diode and the transistor are cascaded.
摘要翻译：半导体结构。半导体包括衬底，第一深阱，二极管和晶体管。第一个深孔在基底上形成。二极管形成在第一个深井中。晶体管形成在第一个深阱中。二极管连接到第一电压，晶体管连接到第二电压，并且二极管和晶体管级联。

7. 发明申请

US20100230749A1 SEMICONDUCTOR DEVICES AND FORMATION METHODS THEREOF 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20100230749A1
公开(公告)日：2010-09-16
申请号：US12574793
申请日：2009-10-07
申请人： Hsin-Chih Chiang , Han-Chung Tai
发明人： Hsin-Chih Chiang , Han-Chung Tai
IPC分类号： H01L27/088 , H01L21/8232
CPC分类号： H01L21/823892 , H01L21/82385 , H01L21/823857 , H01L27/0928
摘要： A semiconductor device is provided and includes a substrate of a first conductivity type, a deep well of a second conductivity type, and a first high-side device. The deep well is formed on the substrate. The first high-side device is disposed within the deep well and includes an insulation layer of the second conductivity type, a well of the first conductivity type, first and second regions of the second conductivity type, and a first poly-silicon material. The insulation layer is formed on the substrate. The well is formed within the deep well. The first and second regions are formed within the well. The first poly-silicon material is disposed between the first region and the second region and on the deep well.
摘要翻译：提供了半导体器件，并且包括第一导电类型的衬底，第二导电类型的阱和第一高侧器件。在衬底上形成深井。第一高侧装置设置在深井内，并且包括第二导电类型的绝缘层，第一导电类型的阱，第二导电类型的第一和第二区域以及第一多晶硅材料。绝缘层形成在基板上。井在深井内形成。第一和第二区域形成在井内。第一多晶硅材料设置在第一区域和第二区域之间以及深井之间。

8. 发明授权

US08492849B2 High side semiconductor structure 有权
标题翻译：高边半导体结构
公开(公告)号：US08492849B2
公开(公告)日：2013-07-23
申请号：US12832727
申请日：2010-07-08
申请人： Han-Chung Tai , Hsin-Chih Chiang
发明人： Han-Chung Tai , Hsin-Chih Chiang
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L21/823892 , H01L27/088 , H01L27/0928 , H01L29/1083
摘要： A high side semiconductor structure is provided. The high side semiconductor structure includes a substrate, a first deep well, a second deep well, a first active element, a second active element and a doped well. The first deep well and the second deep well are formed in the substrate, wherein the first deep well and the second deep well have identical type of ion doping. The first active element and the second active element are respectively formed in the first deep well and the second deep well. The doped well is formed in the substrate and is disposed between the first deep well and the second deep well. The doped well, the first deep well and the second deep well are interspaced, and the type of ion doping of the first deep well and the second deep well is complementary with that of the doped well.
摘要翻译：提供了高边半导体结构。高侧半导体结构包括衬底，第一深阱，第二深阱，第一有源元件，第二有源元件和掺杂阱。在衬底中形成第一深阱和第二深阱，其中第一深阱和第二深阱具有相同类型的离子掺杂。第一有源元件和第二有源元件分别形成在第一深阱和第二深阱中。掺杂阱形成在衬底中并且设置在第一深阱和第二深阱之间。掺杂阱，第一深阱和第二深阱是间隔的，第一深阱和第二深阱的离子掺杂类型与掺杂阱的离子掺杂类型互补。

9. 发明申请

US20110260291A1 Semiconductor Structure 有权
标题翻译：半导体结构
公开(公告)号：US20110260291A1
公开(公告)日：2011-10-27
申请号：US12875455
申请日：2010-09-03
申请人： Han-Chung Tai , Hsin-Chih Chiang
发明人： Han-Chung Tai , Hsin-Chih Chiang
IPC分类号： H01L29/861
CPC分类号： H01L27/0727 , H01L27/0255 , H01L27/0259
摘要： A semiconductor structure. The semiconductor comprises a substrate, a first deep well, a diode and a transistor. The first deep well is formed in the substrate. The diode is formed in the first deep well. The transistor is formed in the first deep well. The diode is connected to a first voltage, the transistor is connected to a second voltage, and the diode and the transistor are cascaded.
摘要翻译：半导体结构。半导体包括衬底，第一深阱，二极管和晶体管。第一个深孔在基底上形成。二极管形成在第一个深井中。晶体管形成在第一个深阱中。二极管连接到第一电压，晶体管连接到第二电压，并且二极管和晶体管级联。

10. 发明授权

US08354698B2 VDMOS and JFET integrated semiconductor device 有权
标题翻译： VDMOS和JFET集成半导体器件
公开(公告)号：US08354698B2
公开(公告)日：2013-01-15
申请号：US12828366
申请日：2010-07-01
申请人： Hsin-Chih Chiang , Han-Chung Tai
发明人： Hsin-Chih Chiang , Han-Chung Tai
IPC分类号： H01L29/80
CPC分类号： H01L27/085 , H01L29/7803 , H01L29/8083
摘要： A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. The first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second source electrode of the JFET respectively.
摘要翻译：半导体器件。半导体包括衬底，VDMOS，JFET，第一电极，第二电极，第三电极和第四电极。 VDMOS形成在基板中。 JFET形成在衬底中。第一电极，第二电极和第三电极分别连接到VDMOS并用作VDMOS的第一栅电极，第一漏电极和第一源电极。第二电极，第三电极和第四电极分别与JFET连接，分别用作JFET的第二漏电极，第二栅电极和第二源电极。

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