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1. 发明申请

US20110102087A1 DC SLOPE GENERATOR 有权
标题翻译：直流斜坡发电机
公开(公告)号：US20110102087A1
公开(公告)日：2011-05-05
申请号：US12610346
申请日：2009-11-02
申请人： Ryan Andrew Jurasek
发明人： Ryan Andrew Jurasek
IPC分类号： H03F3/16
CPC分类号： G05F1/56
摘要： A system for generating a tunable DC slope includes: a first stage, supplied with an external voltage, for receiving a process, voltage and temperature (PVT) insensitive reference voltage and generating a voltage independent current; a second stage, coupled to the first stage and supplied with the external voltage, for generating a voltage dependent current and summing the voltage dependent current and the voltage independent current to generate a sloped voltage; and a third stage, coupled to the second stage and supplied with the external voltage, for amplifying the sloped voltage, and tapping the resultant sloped voltage at a desired point for generating the output DC slope.
摘要翻译：用于产生可调直流斜坡的系统包括：第一级，被提供有外部电压，用于接收过程，电压和温度（PVT）不敏感参考电压并产生不依赖于电压的电流; 第二级，耦合到第一级并提供外部电压，用于产生电压相关电流，并且对电压相关电流和不依赖于电压的电流求和以产生倾斜电压; 以及第三级，耦合到第二级并且被提供有外部电压，用于放大斜坡电压，并且在产生输出DC斜率的期望点上敲击所得到的倾斜电压。

2. 发明授权

US07750684B2 Power-on detection circuit for detecting minimum operational frequency 有权
标题翻译：用于检测最小工作频率的上电检测电路
公开(公告)号：US07750684B2
公开(公告)日：2010-07-06
申请号：US12105280
申请日：2008-04-18
申请人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
发明人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
IPC分类号： G01R23/02 , H03D3/00 , H03K9/06
CPC分类号： H03K3/0315
摘要： A power-on detection circuit for detecting a minimum operational frequency includes: an oscillating circuit, which includes: a ring oscillator, for generating a first oscillating signal; and a high pass filter for filtering the first oscillating signal to generate a second oscillating signal. The power-on detection circuit also includes a rectification device, coupled to the high pass filter, for generating a logic signal once the second oscillating signal reaches a certain frequency.
摘要翻译：用于检测最小工作频率的上电检测电路包括：振荡电路，包括：环形振荡器，用于产生第一振荡信号; 以及高通滤波器，用于对第一振荡信号进行滤波以产生第二振荡信号。上电检测电路还包括耦合到高通滤波器的整流装置，用于在第二振荡信号达到一定频率时产生逻辑信号。

3. 发明申请

US20090237146A1 Dynamic Voltage Pump Circuit and Method of Dynamically Generating an Output Supply Voltage Thereof 有权
标题翻译：动态电压泵电路及动态产生输出电源电压的方法
公开(公告)号：US20090237146A1
公开(公告)日：2009-09-24
申请号：US12050178
申请日：2008-03-18
申请人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
发明人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2001/007
摘要： A dynamic voltage pump circuit includes a first stage voltage pump, a second stage voltage pump, a limiter, and a comparator. The first stage voltage pump generates an intermediate supply voltage according to an input supply voltage and a pump signal. The second stage voltage pump generates an output supply voltage according to the intermediate supply voltage, the pump signal, and an enable signal; the second stage voltage pump is enabled and disabled when the enable signal is asserted and de-asserted, respectively. The limiter controls the pump signal according to a comparison of the output supply voltage with a first reference voltage. The comparator compares the first reference voltage with a second reference voltage to generate the enable signal, and can assert the enable signal when the desired output supply voltage exceeds the maximum possible intermediate supply voltage generated by the first stage voltage pump.
摘要翻译：动态电压泵电路包括第一级电压泵，第二级电压泵，限幅器和比较器。第一级电压泵根据输入电源电压和泵浦信号产生中间电源电压。第二级电压泵根据中间电源电压，泵浦信号和使能信号产生输出电源电压; 当使能信号分别被断言和解除置位时，第二级电压泵被使能和禁止。根据输出电源电压与第一参考电压的比较，限幅器控制泵浦信号。比较器将第一参考电压与第二参考电压进行比较以产生使能信号，并且当期望的输出电源电压超过由第一级电压泵产生的最大可能的中间电源电压时，可以断言使能信号。

4. 发明授权

US08106702B2 Dynamic enabling pump for power control 有权
标题翻译：用于动力控制的动力泵
公开(公告)号：US08106702B2
公开(公告)日：2012-01-31
申请号：US12603572
申请日：2009-10-21
申请人： Ryan Andrew Jurasek
发明人： Ryan Andrew Jurasek
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/073 , H02M2001/0041
摘要： A voltage generation system that can dynamically calibrate a time period for enabling the system includes: a voltage generation circuit, for providing an output voltage; an oscillator, coupled to the voltage generation circuit, for driving the voltage generation circuit to generate the output voltage at a specific frequency according to an enable signal; a limiter, coupled to the oscillator and the output voltage fed back from the voltage generation circuit, for generating the enable signal to the oscillator according to the output voltage; and an enable controller, coupled to the limiter, the oscillator, the voltage generation circuit and the enable signal generated by the limiter, for enabling the limiter, the oscillator and the voltage generation circuit according to an estimated time between enable signals, wherein the estimated time is dynamically calibrated.
摘要翻译：一种电压发生系统，其能够动态地校准用于启用所述系统的时间段，包括：电压产生电路，用于提供输出电压; 耦合到所述电压产生电路的振荡器，用于驱动所述电压产生电路，以根据使能信号以特定频率产生输出电压; 耦合到所述振荡器的限幅器和从所述电压产生电路反馈的输出电压，用于根据所述输出电压向所述振荡器产生使能信号; 以及与限幅器耦合的使能控制器，振荡器，由限幅器产生的电压产生电路和使能信号，用于根据估计的使能信号之间的时间使能限幅器，振荡器和电压产生电路，其中估计的时间是动态校准的。

5. 发明申请

US20110102057A1 TEMPERATURE AND PROCESS DRIVEN REFERENCE 有权
标题翻译：温度和过程驱动参考
公开(公告)号：US20110102057A1
公开(公告)日：2011-05-05
申请号：US12610369
申请日：2009-11-02
申请人： Ryan Andrew Jurasek , Richard Michael Parent
发明人： Ryan Andrew Jurasek , Richard Michael Parent
IPC分类号： H01L37/00
CPC分类号： G05F1/567
摘要： A reference voltage generation circuit for generating a reference voltage that can adaptively depend on temperature and process includes: a comparator, having a process, temperature and voltage (PVT) insensitive reference as a first input, and a feedback of the output as a second input, for generating a voltage reference output; a first resistor, coupled to the output of the operational amplifier; a second and a third variable resistor coupled in parallel, and coupled between the first resistor and ground; and a transistor, coupled between the third variable resistor and ground.
摘要翻译：用于产生可以自适应地依赖于温度和过程的参考电压的参考电压产生电路包括：具有作为第一输入的过程，温度和电压（PVT）不敏感参考值的比较器，以及作为第二输入的输出的反馈，用于产生电压参考输出; 耦合到运算放大器的输出的第一电阻器; 并联耦合的第二和第三可变电阻器，并且耦合在第一电阻器和地之间; 以及耦合在第三可变电阻器和地之间的晶体管。

6. 发明授权

US07663418B2 Driving circuit slew rate compensation method 有权
标题翻译：驱动电路转换速率补偿方法
公开(公告)号：US07663418B2
公开(公告)日：2010-02-16
申请号：US11969209
申请日：2008-01-03
申请人： Bret Roberts Dale , Ryan Andrew Jurasek , Darin James Daudelin , Dave Eugene Chapmen
发明人： Bret Roberts Dale , Ryan Andrew Jurasek , Darin James Daudelin , Dave Eugene Chapmen
IPC分类号： H03K5/12
CPC分类号： H03K17/00 , H03K5/00
摘要： An apparatus for compensating slew rate of a driving circuit includes: a first circuit, for receiving an edge transition from the driving circuit and generating a first pulse proportional to an actual slope of the edge transition; a second circuit, for receiving an ideal edge transition of the driving circuit and generating a second pulse proportional to an ideal slope of the ideal edge transition; a comparison circuit, coupled to the first circuit and the second circuit, for comparing an extreme value of amplitude of the first pulse with an extreme value of amplitude of the second pulse to produce a comparison signal; and a control circuit, coupled to the comparison circuit, for increasing or decreasing the slew rate of the driving circuit according to the comparison signal.
摘要翻译：一种用于补偿驱动电路的转换速率的装置包括：第一电路，用于接收来自驱动电路的边沿转变并产生与边沿跃迁的实际斜率成比例的第一脉冲; 第二电路，用于接收驱动电路的理想边沿转变并产生与理想边沿跃迁的理想斜率成比例的第二脉冲; 耦合到第一电路和第二电路的比较电路，用于将第一脉冲的幅度的极值与第二脉冲的极值的极值进行比较，以产生比较信号; 以及耦合到比较电路的控制电路，用于根据比较信号增加或减小驱动电路的转换速率。

7. 发明授权

US07633331B2 Dynamic voltage pump circuit and method of dynamically generating an output supply voltage thereof 有权
标题翻译：动态电压泵电路及动态产生其输出电源电压的方法
公开(公告)号：US07633331B2
公开(公告)日：2009-12-15
申请号：US12050178
申请日：2008-03-18
申请人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
发明人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2001/007
摘要： A dynamic voltage pump circuit includes a first stage voltage pump, a second stage voltage pump, a limiter, and a comparator. The first stage voltage pump generates an intermediate supply voltage according to an input supply voltage and a pump signal. The second stage voltage pump generates an output supply voltage according to the intermediate supply voltage, the pump signal, and an enable signal; the second stage voltage pump is enabled and disabled when the enable signal is asserted and de-asserted, respectively. The limiter controls the pump signal according to a comparison of the output supply voltage with a first reference voltage. The comparator compares the first reference voltage with a second reference voltage to generate the enable signal, and can assert the enable signal when the desired output supply voltage exceeds the maximum possible intermediate supply voltage generated by the first stage voltage pump.
摘要翻译：动态电压泵电路包括第一级电压泵，第二级电压泵，限幅器和比较器。第一级电压泵根据输入电源电压和泵浦信号产生中间电源电压。第二级电压泵根据中间电源电压，泵浦信号和使能信号产生输出电源电压; 当使能信号分别被断言和解除置位时，第二级电压泵被使能和禁止。根据输出电源电压与第一参考电压的比较，限幅器控制泵浦信号。比较器将第一参考电压与第二参考电压进行比较以产生使能信号，并且当期望的输出电源电压超过由第一级电压泵产生的最大可能的中间电源电压时，可以断言使能信号。

8. 发明授权

US08102690B2 Bank re-assignment in chip to reduce IR drop 有权
标题翻译：银行重新分配芯片以减少IR下降
公开(公告)号：US08102690B2
公开(公告)日：2012-01-24
申请号：US12577704
申请日：2009-10-12
申请人： Richard Michael Parent , Ryan Andrew Jurasek , Dave Eugene Chapmen
发明人： Richard Michael Parent , Ryan Andrew Jurasek , Dave Eugene Chapmen
IPC分类号： G11C5/00 , G11C8/00 , G06F11/06
CPC分类号： G11C7/1018 , G11C5/025 , G11C7/1045 , G11C2207/105
摘要： A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.
摘要翻译：在特定操作模式下降低功耗的芯片系统包括：DDR3芯片，包括：设置在DDR3芯片中心的多个焊盘; 和一组银行，每个银行都有一个特定的逻辑地址，围绕着这些垫。芯片系统还包括：耦合到DDR3芯片的时钟，用于控制数据传输速率; 以及存储器控制器，其耦合到时钟，用于根据特定操作模式来协调与相关过程的传输数据，并且用于选择性地重新分配存储体逻辑地址。

9. 发明授权

US07940549B2 DRAM positive wordline voltage compensation device for array device threshold voltage and voltage compensating method thereof 有权
标题翻译：用于阵列器件阈值电压及其电压补偿方法的DRAM正字线电压补偿装置
公开(公告)号：US07940549B2
公开(公告)日：2011-05-10
申请号：US12573486
申请日：2009-10-05
申请人： Benjamin James Stembridge , Ryan Andrew Jurasek , Richard Michael Parent
发明人： Benjamin James Stembridge , Ryan Andrew Jurasek , Richard Michael Parent
IPC分类号： G11C11/24
CPC分类号： G11C11/4085 , G11C8/08 , G11C11/4074
摘要： The configurations of a DRAM positive wordline voltage compensation device and a voltage compensating method thereof are provided in the present invention. The proposed device includes a comparator having a first input terminal receiving a positive wordline voltage feedback signal, a second input terminal receiving a compensating reference of array device threshold voltage and an output terminal generating a first enable signal, an oscillator receiving the first enable signal and generating an oscillating signal when the first enable signal is active and a charge pump having a first input terminal receiving a second enable signal, a second input terminal receiving the oscillating signal and an output terminal generating a positive wordline voltage being a sum of a bitline high voltage, an array device threshold voltage and a voltage margin.
摘要翻译：在本发明中提供了DRAM正字线电压补偿装置及其电压补偿方法的结构。所提出的装置包括比较器，其具有接收正字线电压反馈信号的第一输入端，接收阵列器件阈值电压的补偿参考的第二输入端和产生第一使能信号的输出端，接收第一使能信号的振荡器和当所述第一使能信号有效时产生振荡信号，以及具有接收第二使能信号的第一输入端的电荷泵，接收所述振荡信号的第二输入端子以及产生正字线电压的输出端子，所述正极线电压是位线高电压，阵列器件阈值电压和电压裕度。

10. 发明申请

US20110085402A1 BANK RE-ASSIGNMENT IN CHIP TO REDUCE IR DROP 有权
标题翻译：银行重新分配，以减少红外线
公开(公告)号：US20110085402A1
公开(公告)日：2011-04-14
申请号：US12577704
申请日：2009-10-12
申请人： Richard Michael Parent , Ryan Andrew Jurasek , Dave Eugene Chapmen
发明人： Richard Michael Parent , Ryan Andrew Jurasek , Dave Eugene Chapmen
IPC分类号： G11C8/00 , G11C5/14 , G11C8/16
CPC分类号： G11C7/1018 , G11C5/025 , G11C7/1045 , G11C2207/105
摘要： A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the centre of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.
摘要翻译：在特定操作模式下降低功耗的芯片系统包括：DDR3芯片，包括：设置在DDR3芯片中心的多个焊盘; 和一组银行，每个银行都有一个特定的逻辑地址，围绕着这些垫。芯片系统还包括：耦合到DDR3芯片的时钟，用于控制数据传输速率; 以及存储器控制器，其耦合到时钟，用于根据特定操作模式来协调与相关过程的传输数据，并且用于选择性地重新分配存储体逻辑地址。

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