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1. 发明授权

US07984403B2 Verification supporting system 有权
标题翻译：验证支持系统
公开(公告)号：US07984403B2
公开(公告)日：2011-07-19
申请号：US12359105
申请日：2009-01-23
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

2. 发明申请

US20090276740A1 VERIFICATION SUPPORTING APPARATUS, VERIFICATION SUPPORTING METHOD, AND COMPUTER PRODUCT 有权
标题翻译：验证支持设备，验证支持方法和计算机产品
公开(公告)号：US20090276740A1
公开(公告)日：2009-11-05
申请号：US12335105
申请日：2008-12-15
申请人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
发明人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.
摘要翻译：在验证支持装置中，记录单元记录其中可能发生在待验证电路的寄存器中可能发生的状态转换的DIRW矩阵和关于与状态转换相对应的路径的有效性的信息，并且获取单元获取控制数据流图包括其中写入数据流图的控制流图。当指定用于验证的寄存器时，从控制数据流程图中提取其中描述的指定寄存器的数据流图。从提取的数据流图中，提取指示关于寄存器的数据流的路径。识别提取的路径的状态转换，并且如果在DIRW矩阵中设置状态转换，则将与DIRW矩阵和路径中设置的有效性有关的信息相关并输出。

3. 发明授权

US08312400B2 Verification supporting system 有权
标题翻译：验证支持系统
公开(公告)号：US08312400B2
公开(公告)日：2012-11-13
申请号：US13157534
申请日：2011-06-10
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

4. 发明申请

US20110239172A1 VERIFICATION SUPPORTING SYSTEM 有权
标题翻译：验证支持系统
公开(公告)号：US20110239172A1
公开(公告)日：2011-09-29
申请号：US13157534
申请日：2011-06-10
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

5. 发明授权

US08015519B2 Verification supporting apparatus, verification supporting method, and computer product 有权
标题翻译：验证支持设备，验证支持方式和计算机产品
公开(公告)号：US08015519B2
公开(公告)日：2011-09-06
申请号：US12335105
申请日：2008-12-15
申请人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
发明人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.
摘要翻译：在验证支持装置中，记录单元记录其中可能发生在待验证电路的寄存器中可能发生的状态转换的DIRW矩阵和关于与状态转换相对应的路径的有效性的信息，并且获取单元获取控制数据流图包括其中写入数据流图的控制流图。当指定用于验证的寄存器时，从控制数据流程图中提取其中描述的指定寄存器的数据流图。从提取的数据流图中，提取指示关于寄存器的数据流的路径。识别提取的路径的状态转换，并且如果在DIRW矩阵中设置状态转换，则将与DIRW矩阵和路径中设置的有效性有关的信息相关并输出。

6. 发明申请

US20090287965A1 VERIFICATION SUPPORTING SYSTEM 有权
标题翻译：验证支持系统
公开(公告)号：US20090287965A1
公开(公告)日：2009-11-19
申请号：US12359105
申请日：2009-01-23
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F11/34
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证对象电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定的验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

7. 发明授权

US08370781B2 Computer product for supporting design and verification of integrated circuit 有权
公开(公告)号：US08370781B2
公开(公告)日：2013-02-05
申请号：US11896301
申请日：2007-08-30
申请人： Ryosuke Oishi , Akio Matsuda
发明人： Ryosuke Oishi , Akio Matsuda
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step; converting the activity diagram to a second use case diagram representing a function of the object, based on the structure analyzed at the analyzing; verifying uniformity of the first use case diagram and the second use case diagram; and outputting a verification result obtained at the verifying uniformity.

8. 发明申请

US20100064266A1 VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT 有权
标题翻译：验证支持设备，验证支持方法和计算机产品
公开(公告)号：US20100064266A1
公开(公告)日：2010-03-11
申请号：US12484762
申请日：2009-06-15
申请人： Akio Matsuda , Ryosuke Oishi
发明人： Akio Matsuda , Ryosuke Oishi
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a combinational circuit to be verified; extracting, from the hardware description, a conditional branch description expressing conditional branch processing; identifying, from among conditional branch descriptions extracted at the extracting of a conditional branch description and based on a description sequence in the hardware description, a combination of conditional branch descriptions having a hierarchical relation; extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy a specified condition; creating a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted at the extracting of the combination to be satisfied; and outputting, as assertion information of the combinational circuit, the simulation program created for each combination at the creating.
摘要翻译：计算机可读记录介质中存储有使计算机执行接收要验证的组合电路的硬件描述的验证支持程序; 从硬件描述中提取表示条件分支处理的条件分支描述; 从提取条件分支描述中提取的条件分支描述中，根据硬件描述中的描述序列，识别具有分层关系的条件分支描述的组合; 从识别中识别的条件分支描述的组合中提取具有满足指定条件的潜力的组合; 创建一个模拟程序，导致包含在组合提取中提取的组合中的条件分支描述的指定条件得到满足; 并且作为组合电路的断言信息输出在创建时为每个组合创建的模拟程序。

9. 发明申请

US20080263485A1 Verification support method and apparatus, and computer product 有权
标题翻译：验证支持方法和设备，以及计算机产品
公开(公告)号：US20080263485A1
公开(公告)日：2008-10-23
申请号：US12081417
申请日：2008-04-15
申请人： Akio Matsuda , Ryosuke Oishi
发明人： Akio Matsuda , Ryosuke Oishi
IPC分类号： G06F17/50
CPC分类号： G06F11/261
摘要： A verification support apparatus that verifies operation of a circuit includes a receiving unit, a detecting unit, and a determining unit. The receiving unit receives implementation description data of the circuit. Based on the implementation description data, the detecting unit detects a functional block that is in the circuit and includes an external input terminal that receives an external input signal. Based on a detection result of the detecting unit, the determining unit determines the functional block to verify an abnormal-event operation. The abnormal-event operation is an operation that differs from an operation implementing a function of the circuit.
摘要翻译：验证电路的操作的验证支持装置包括接收单元，检测单元和确定单元。接收单元接收电路的实现描述数据。基于实现描述数据，检测单元检测电路中的功能块，并且包括接收外部输入信号的外部输入端子。基于检测单元的检测结果，确定单元确定功能块以验证异常事件操作。异常事件操作是与实现电路功能的操作不同的操作。

10. 发明申请

US20120240120A1 INFORMATION PROCESSING APPARATUS, POWER CONTROL METHOD, AND COMPUTER PRODUCT 有权
标题翻译：信息处理装置，功率控制方法和计算机产品
公开(公告)号：US20120240120A1
公开(公告)日：2012-09-20
申请号：US13332887
申请日：2011-12-21
申请人： Akio Matsuda , Ryosuke Oishi
发明人： Akio Matsuda , Ryosuke Oishi
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , G06F1/3206 , Y02D10/24
摘要： An information processing apparatus includes a first detector that detects a scheduled starting time of an event to be corrected and executed at the current time or thereafter; a second detector that detects in processing contents differing from that of the event detected by the first detector, a scheduled starting time of each event to be executed at the current time or thereafter; a calculator that calculates the difference between the scheduled starting time detected by the first detector and each scheduled starting time detected by the second detector; a determiner that determines a target event for the event to be corrected, based on the calculated differences; and a corrector that corrects the scheduled starting time of the event to be corrected such that an interval becomes short between the scheduled starting time of the event to be corrected and the scheduled starting time of the target event.
摘要翻译：信息处理设备包括：第一检测器，其检测在当前时间或之后要被校正和执行的事件的预定开始时间; 处理与第一检测器检测到的事件不同的内容的第二检测器，在当前时间或之后执行的每个事件的调度开始时间; 计算器，其计算由所述第一检测器检测到的所述预定开始时间与由所述第二检测器检测到的每个调度的开始时间之间的差; 基于所计算的差异来确定要校正的事件的目标事件的确定器; 以及校正器，其校正要校正的事件的预定开始时间，使得在待校正的事件的调度的开始时间与目标事件的调度的开始时间之间的间隔变短。

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