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1. 发明授权

US10803925B2 Sense amplifier having offset cancellation 有权
公开(公告)号：US10803925B2
公开(公告)日：2020-10-13
申请号：US16829044
申请日：2020-03-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Young-Wook Kim , Hyuk-Joon Kwon , Sang-Keun Han , Bok-Yeon Won
IPC分类号： G11C11/4091 , G11C7/06 , G11C11/4094 , G11C11/4097 , G11C5/02 , G11C7/02 , G11C5/06 , G11C11/4096 , G11C11/408
摘要： A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

2. 发明授权

US11127789B2 Magnetic memory devices 有权
公开(公告)号：US11127789B2
公开(公告)日：2021-09-21
申请号：US16887541
申请日：2020-05-29
申请人： Samsung Electronics Co., Ltd.
发明人： Han-Na Cho , Bok-Yeon Won , Oik Kwon
IPC分类号： H01L27/22 , H01L43/02 , H01L23/528 , H01L23/522 , H01L43/10
摘要： A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

3. 发明授权

US11043257B2 Sense amplifier having offset cancellation 有权
公开(公告)号：US11043257B2
公开(公告)日：2021-06-22
申请号：US16989207
申请日：2020-08-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Young-Wook Kim , Hyuk-Joon Kwon , Sang-Keun Han , Bok-Yeon Won
IPC分类号： G11C11/4091 , G11C5/02 , G11C7/02 , G11C11/4094 , G11C11/4097 , G11C11/4096 , G11C11/408 , G11C5/06 , G11C7/06
摘要： A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

4. 发明申请

US20220406360A1 SUB-WORD-LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME 有权
公开(公告)号：US20220406360A1
公开(公告)日：2022-12-22
申请号：US17685849
申请日：2022-03-03
申请人： Samsung Electronics Co., Ltd.
发明人： Seokjae Lee , Bok-Yeon Won , Kyoungmin Kim , Donggeon Kim , Myeongsik Ryu , Sangwook Park , Inseok Baek
IPC分类号： G11C11/408 , H01L27/108
摘要： A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

5. 发明授权

US10755765B2 Layout structure of a bit line sense amplifier in a semiconductor memory device 有权
公开(公告)号：US10755765B2
公开(公告)日：2020-08-25
申请号：US16116079
申请日：2018-08-29
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Bok-Yeon Won , Hyuck-Joon Kwon
IPC分类号： G11C11/34 , G11C11/4091 , G11C7/08 , G11C7/18 , G11C8/14 , G11C11/408 , G11C11/4097 , G11C5/02 , G11C7/02 , G11C11/4094
摘要： A layout structure of a bit line sense amplifier in a semiconductor memory device includes a first bit line sense amplifier which is connected to a first bit line and a first complementary bit line, and is controlled via a first control line and a second control line. The first control line is connected to a first node of the first bit line sense amplifier and the second control line is connected to a second node of the first bit line sense amplifier, and the first bit line sense amplifier includes at least one pair of transistors configured to share any one of a first active region corresponding to the first node and a second active region corresponding to the second node.

6. 发明授权

US10541022B2 Sense amplifier having offset cancellation 有权
公开(公告)号：US10541022B2
公开(公告)日：2020-01-21
申请号：US16256883
申请日：2019-01-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Young-Wook Kim , Hyuk-Joon Kwon , Sang-Keun Han , Bok-Yeon Won
IPC分类号： G11C5/02 , G11C5/06 , G11C7/06 , G11C11/4091 , G11C7/02 , G11C11/4094 , G11C11/4097 , G11C11/4096 , G11C11/408
摘要： A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

7. 发明授权

US09318169B2 Bit line equalizing circuit 有权
标题翻译：位线均衡电路
公开(公告)号：US09318169B2
公开(公告)日：2016-04-19
申请号：US14326543
申请日：2014-07-09
申请人： Samsung Electronics Co., Ltd.
发明人： Bok-Yeon Won , Hyuk-Joon Kwon
IPC分类号： G11C7/00 , G11C7/12 , G11C11/4094 , H01L27/02 , H01L27/108
CPC分类号： G11C7/12 , G11C11/4094 , H01L27/0207 , H01L27/10897
摘要： There is provided a bit line equalizing circuit including: an active region; a first bit line disposed on the active region in a first direction; a second bit line disposed on the active region in the first direction; a gate pattern including a first pattern disposed on the active region in a second direction crossing the first direction, and a second pattern extended from one side of the first pattern to be disposed in the first direction, and formed in a stair shape; a first contact disposed at one side of the first pattern and one side of the second pattern, and configured to connect the active region and the first bit line; a second contact disposed at one side of the first pattern and the other side of the second pattern, and configured to connect the active region and the second bit line; and a third contact disposed at the other side of the first pattern, and configured to provide a predetermined voltage to the active region.
摘要翻译：提供了一种位线均衡电路，包括：有源区; 在第一方向上设置在有源区上的第一位线; 在所述有源区域上沿所述第一方向设置的第二位线; 形成在第一方向上的第二方向上的第一图案和从第一图案的一侧向第一方向延伸的第二图案，形成为阶梯状; 第一触点，其设置在所述第一图案的一侧和所述第二图案的一侧，并且被配置为连接所述有源区域和所述第一位线; 设置在所述第一图案的一侧和所述第二图案的另一侧的第二触点，并且被配置为连接所述有源区域和所述第二位线; 以及设置在所述第一图案的另一侧的第三触点，并且被配置为向所述有源区域提供预定电压。

8. 发明授权

US10692565B2 Sense amplifier having offset cancellation 有权
公开(公告)号：US10692565B2
公开(公告)日：2020-06-23
申请号：US16707738
申请日：2019-12-09
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Young-Wook Kim , Hyuk-Joon Kwon , Sang-Keun Han , Bok-Yeon Won
IPC分类号： G11C11/4091 , G11C7/06 , G11C11/4097 , G11C11/4094 , G11C7/02 , G11C5/02 , G11C11/4096 , G11C5/06 , G11C11/408
摘要： A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

9. 发明申请

US20190189186A1 SUB-WORD LINE DRIVERS AND RELATED SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：US20190189186A1
公开(公告)日：2019-06-20
申请号：US16034604
申请日：2018-07-13
申请人： Samsung Electronics Co., Ltd.
发明人： Bok-Yeon Won , Hyuckjoon Kwon
IPC分类号： G11C11/408 , H01L27/02 , H01L27/108
CPC分类号： G11C11/4085 , H01L27/0207 , H01L27/10805
摘要： Semiconductor memory devices are provided. A semiconductor memory device includes a first keeper transistor that is connected to a first word line. The semiconductor memory device includes a second keeper transistor that is connected to a second word line. The first keeper transistor and the second keeper transistor have a merged channel. In some embodiments, the first keeper transistor and the second keeper transistor are in a sub-word line driver.

10. 发明授权

US10262935B2 Memory device and method of disposing conduction lines of the same 有权
公开(公告)号：US10262935B2
公开(公告)日：2019-04-16
申请号：US15677054
申请日：2017-08-15
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Ju Kim , Su-A Kim , Soo-Young Kim , Min-Woo Won , Bok-Yeon Won , Ji-Suk Kwon , Young-Ho Kim , Ji-Hak Yu , Hyun-Chul Yoon , Seok-Jae Lee , Sang-Keun Han , Woong-Dai Kang , Hyuk-Joon Kwon , Bum-Jae Lee
IPC分类号： H01L23/522 , G11C11/408 , G11C11/4091 , G11C11/4097 , H01L23/528 , H01L23/00 , H01L23/50 , H01L23/552 , G11C7/10 , G11C7/06
摘要： A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

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