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1. 发明授权

US10521959B2 Methods of and devices for reducing structure noise through self-structure analysis 有权
公开(公告)号：US10521959B2
公开(公告)日：2019-12-31
申请号：US15687605
申请日：2017-08-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Je-Hyun Lee , Sung-Hwan Jang , Sung-Youn Chung , Jae-Hoon Jeong
IPC分类号： G06F17/30 , G06T17/20 , G06K9/62 , G06K9/00 , G06K9/40 , G06T19/20
摘要： To reduce structure noise, input data representing an input structure is obtained and boundary conditions are set by classifying data of each of multiple structure elements of the input data as a signal component or a noise component. A smoothing operation is performed with respect to the input data and based on the boundary conditions. Output data representing an output structure is provided by reducing noise from the input structure.

2. 发明授权

US08856714B2 Method and system for designing 3D semiconductor package 有权
标题翻译：三维半导体封装设计方法及系统
公开(公告)号：US08856714B2
公开(公告)日：2014-10-07
申请号：US13803534
申请日：2013-03-14
申请人： Samsung Electronics Co., Ltd.
发明人： Bo-Sun Hwang , Sung-Hee Yun , Jae-Hoon Jeong , Won-Cheol Lee , Tae-Heon Lee , Young-Hoe Cheon
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5077 , G06F19/00 , G06F2217/12 , G06F2217/14
摘要： A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.
摘要翻译：三维半导体封装及其制造方法包括为包括在第一封装中的多个第一端子提供第一封装布局参数，第二封装布局参数，用于包括在第二封装中的第二封装中的多个第二封装，以及用于电连接第一封装和第二封装的多个连接端子的连接端子布局参数; 通过对第一封装，第二封装和连接端子布局参数施加第一工艺，在第一和第二端子与连接端子之间提供第一布线连接布局; 以及通过将不同于第一处理的第二处理与第一布线连接布局，在第一和第二端子与连接端子之间提供第二布线连接布局。

3. 发明授权

US08832638B2 Package test devices having a printed circuit board 有权
标题翻译：具有印刷电路板的封装测试装置
公开(公告)号：US08832638B2
公开(公告)日：2014-09-09
申请号：US13780891
申请日：2013-02-28
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Hoon Jeong , Chang-Woo Ko , Ki-Jae Song , Hun-Kyo Seo
IPC分类号： G06F17/50 , G01R1/04 , G01R31/28 , G11C29/56
CPC分类号： G01R1/0408 , G01R31/2808 , G06F17/5068 , G11C29/56 , G11C2029/5602
摘要： In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.
摘要翻译：在设计印刷电路板的方法中，计算实际存储器件的封装电容，封装电感和芯片电容。基于印刷电路板的特性来计算信号线的每单位长度的信号线电容和信号线电感。基于封装电容和信号线电容确定每个引脚的信号线的长度。

4. 发明申请

US20140208284A1 METHOD AND SYSTEM FOR DESIGNING 3D SEMICONDUCTOR PACKAGE 有权
标题翻译：用于设计3D半导体封装的方法和系统
公开(公告)号：US20140208284A1
公开(公告)日：2014-07-24
申请号：US13803534
申请日：2013-03-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Bo-Sun Hwang , Sung-Hee Yun , Jae-Hoon Jeong , Won-Cheol Lee , Tae-Heon Lee , Young-Hoe Cheon
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F19/00 , G06F2217/12 , G06F2217/14
摘要： A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.
摘要翻译：三维半导体封装及其制造方法包括为包括在第一封装中的多个第一端子提供第一封装布局参数，第二封装布局参数，用于包括在第二封装中的第二封装中的多个第二封装，以及用于电连接第一封装和第二封装的多个连接端子的连接端子布局参数; 通过对第一封装，第二封装和连接端子布局参数施加第一工艺，在第一和第二端子与连接端子之间提供第一布线连接布局; 以及通过将不同于第一处理的第二处理与第一布线连接布局，在第一和第二端子与连接端子之间提供第二布线连接布局。

5. 发明申请

US20130176045A1 PACKAGE TEST DEVICES HAVING A PRINTED CIRCUIT BOARD 有权
标题翻译：具有印刷电路板的封装测试装置
公开(公告)号：US20130176045A1
公开(公告)日：2013-07-11
申请号：US13780891
申请日：2013-02-28
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Hoon Jeong , Chang-Woo Ko , Ki-Jae Song , Hun-Kyo Seo
IPC分类号： G01R1/04
CPC分类号： G01R1/0408 , G01R31/2808 , G06F17/5068 , G11C29/56 , G11C2029/5602
摘要： In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.
摘要翻译：在设计印刷电路板的方法中，计算实际存储器件的封装电容，封装电感和芯片电容。基于印刷电路板的特性来计算信号线的每单位长度的信号线电容和信号线电感。基于封装电容和信号线电容确定每个引脚的信号线的长度。

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