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1. 发明授权

US11627021B2 Data processing device and memory system including the same 有权
公开(公告)号：US11627021B2
公开(公告)日：2023-04-11
申请号：US17563406
申请日：2021-12-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jaewoo Park , Youngdon Choi , Junghwan Choi , Changsik Yoo
IPC分类号： H04L25/02 , H04L25/14 , H04L25/49
摘要： Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.

2. 发明申请

US20230099738A1 HIGH RESOLUTION PHASE CORRECTING CIRCUIT AND PHASE INTERPOLATING DEVICE 有权
公开(公告)号：US20230099738A1
公开(公告)日：2023-03-30
申请号：US17872527
申请日：2022-07-25
申请人： Samsung Electronics Co., Ltd.
发明人： Jinook Jung , Jaewoo Park , Myoungbo Kwak , Junghwan Choi
IPC分类号： H03K5/01 , H03H11/16
摘要： A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.

3. 发明授权

US11594267B2 Memory device for receiving one clock signal as a multi-level signal and restoring original data encoded into the clock signal and method of operating the same 有权
公开(公告)号：US11594267B2
公开(公告)日：2023-02-28
申请号：US17230403
申请日：2021-04-14
申请人： Samsung Electronics Co., Ltd.
发明人： Mingyu Lee , Jaewoo Park , Younghoon Son , Youngdon Choi , Hyungmin Jin , Junghwan Choi
IPC分类号： G11C7/22 , G11C7/06 , G06F13/16
摘要： A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

4. 发明授权

US09899075B2 Multi channel semiconductor device having multi dies and operation method thereof 有权
公开(公告)号：US09899075B2
公开(公告)日：2018-02-20
申请号：US14795191
申请日：2015-07-09
申请人： Samsung Electronics Co., Ltd.
发明人： Yoon-Joo Eom , Joon-Young Park , Yongcheol Bae , Won Young Lee , Seongjin Jang , Junghwan Choi , Joosun Choi
IPC分类号： G11C5/06 , G11C11/4096 , G11C11/4093 , G11C7/10
CPC分类号： G11C11/4096 , G11C7/1084 , G11C11/4093 , G11C2207/105
摘要： A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.

5. 发明授权

US09524761B2 Semiconductor device including latch controller for preventing DC current from flowing between differential signals and method of operating same 有权
标题翻译：包括用于防止DC电流在差分信号之间流动的闩锁控制器的半导体装置及其操作方法
公开(公告)号：US09524761B2
公开(公告)日：2016-12-20
申请号：US14731787
申请日：2015-06-05
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Won Young Lee , Yongcheol Bae , Junghwan Choi
IPC分类号： G11C7/10 , G11C7/06 , G11C7/00 , G11C7/02
CPC分类号： G11C7/1087 , G11C7/1084
摘要： Provided is a semiconductor device to prevent DC current from flowing between differential input signals. The semiconductor device includes a first input unit configured to buffer a first signal of differential input signals, a second input configured to buffer a second signal of the differential input signals, and a latch coupled between a first repeating node of the first input unit and a second repeating node of the second input unit to prevent duty variation of the first and second signals. The semiconductor device further includes a latch controller configured to selectively switch the operation of the latch based on states of the first and second signals appearing at the first and second repeating nodes during a time interval before preambles of the differential input signals are received.
摘要翻译：提供了防止直流电流在差分输入信号之间流动的半导体器件。半导体器件包括被配置为缓冲差分输入信号的第一信号的第一输入单元，被配置为缓冲差分输入信号的第二信号的第二输入，以及耦合在第一输入单元的第一中继节点与第一输入单元之间的锁存器第二输入单元的第二重复节点，以防止第一和第二信号的占空比变化。半导体器件还包括锁存器控制器，其被配置为基于在接收差分输入信号的前导码之前的时间间隔期间基于出现在第一和第二重复节点处的第一和第二信号的状态来选择性地切换锁存器的操作。

6. 发明申请

US20230120821A1 RECEIVER FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME 有权
公开(公告)号：US20230120821A1
公开(公告)日：2023-04-20
申请号：US17827126
申请日：2022-05-27
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HYUNSUB RIE , Eunseok Shin , Youngdon Choi , Changsoo Yoon , Hyunyoon Cho , Junghwan Choi
IPC分类号： G11C7/06 , G11C7/10 , G11C7/14
摘要： A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.

7. 发明授权

US11587598B2 Memory device for generating pulse amplitude modulation-based DQ signal and memory system including the same 有权
公开(公告)号：US11587598B2
公开(公告)日：2023-02-21
申请号：US17385002
申请日：2021-07-26
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Youngdo Um , Younghoon Son , Youngdon Choi , Jindo Byun , Hyunyoon Cho , Junghwan Choi
IPC分类号： H04B1/00 , G11C7/10 , H04L25/49
摘要： A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.

8. 发明授权

US11483512B2 Display apparatus and operation method thereof 有权
公开(公告)号：US11483512B2
公开(公告)日：2022-10-25
申请号：US17119329
申请日：2020-12-11
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Taehwan Kim , Sungjin Son , Seungjin Park , Kwangsub Byun , Junghwan Choi , Byungkwon Kang , Seokjae Lee
IPC分类号： H04N5/445 , H04N21/431
摘要： Provided are a display apparatus and an operation method thereof for preventing image flicker when displaying mixed images: generating a first image corresponding to video content on a first plane, generating, on a second plane, a second image, outputting a mixed image that is a mixture of the first image and the second image, generating a third image on a third plane corresponding to the mixed image, and displaying the third image based on removal of the first image from the display.

9. 发明申请

US20220076715A1 MEMORY DEVICES CONFIGURED TO GENERATE PULSE AMPLITUDE MODULATION-BASED DQ SIGNALS, MEMORY CONTROLLERS, AND MEMORY SYSTEMS INCLUDING THE MEMORY DEVICES AND THE MEMORY CONTROLLERS 有权
公开(公告)号：US20220076715A1
公开(公告)日：2022-03-10
申请号：US17347998
申请日：2021-06-15
申请人： Samsung Electronics Co., Ltd.
发明人： Sucheol Lee , Younghoon Son , Hyunyoon Cho , Youngdon Choi , Junghwan Choi
IPC分类号： G11C7/10 , H03K19/017 , H03K7/02
摘要： A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.

10. 发明申请

US20220075725A1 TRANSMITTERS FOR GENERATING MULTI-LEVEL SIGNALS AND MEMORY SYSTEM INCLUDING THE SAME 有权
公开(公告)号：US20220075725A1
公开(公告)日：2022-03-10
申请号：US17320460
申请日：2021-05-14
申请人： Samsung Electronics Co., Ltd.
发明人： Hyungmin Jin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC分类号： G06F12/0802 , G11C7/10 , H03K19/00 , G11C8/06 , H03K19/0185
摘要： A multi-level signal transmitter includes a voltage selection circuit, which is configured to select one amongst a plurality of driving voltages, which have different voltage levels, in response to input data including at least two bits of data therein. A driver circuit is also provided, which is configured to generate an output data signal as a multi-level signal, in response to the selected one of the plurality of driving voltages. This selected signal is provided as a body bias voltage to at least one transistor within the driver circuit. This driver circuit may include a totem-pole arrangement of first and second MOS transistors having respective first and second body bias regions therein, and at least one of the first and second body bias regions may be responsive to the selected one of the plurality of driving voltages.

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