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1. 发明公开

US20230361112A1 BIPOLAR JUNCTION TRANSISTORS AND P-N JUNCTION DIODES INCLUDING STACKED NANO-SEMICONDUCTOR LAYERS 审中-公开
公开(公告)号：US20230361112A1
公开(公告)日：2023-11-09
申请号：US17936127
申请日：2022-09-28
申请人： Samsung Electronics Co.; Ltd.
发明人： BYOUNGHAK HONG , Gunho Jo , Sooyoung Park , Hyoeun Park , WookHyun Kwon , Jaehong Lee , Kang-Ill Seo
IPC分类号： H01L27/06 , H01L29/06 , H01L29/735 , H01L29/861
CPC分类号： H01L27/067 , H01L29/0673 , H01L29/735 , H01L29/8613
摘要： Integrated circuit devices including a bipolar junction transistor (BJT) and/or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.

2. 发明授权

US11322602B2 Vertical field-effect transistor (VFET) devices and methods of forming the same 有权
公开(公告)号：US11322602B2
公开(公告)日：2022-05-03
申请号：US16794358
申请日：2020-02-19
申请人： Samsung Electronics Co., Ltd.
发明人： Hwi Chan Jun , Kang-Ill Seo , Jeong Hyuk Yim
IPC分类号： H01L29/66 , H01L29/78
摘要： Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity.

3. 发明授权

US09614068B2 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US09614068B2
公开(公告)日：2017-04-04
申请号：US14843231
申请日：2015-09-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kang-Ill Seo
IPC分类号： H01L29/06 , H01L29/775 , H01L29/423 , H01L29/786
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/78696
摘要： A semiconductor device includes a first active region, a field insulating layer disposed in the first active region, a first nanowire pattern disposed on the first active region and extended in a first direction, and a first gate disposed on the first active region and extended in a second direction crossing the first direction. The first gate covers the first nanowire pattern. The semiconductor device further includes a source or drain epitaxial layer disposed on at least one side of the first nanowire pattern. The first gate includes a first region disposed on the first nanowire pattern and having a first width, and a second region disposed beneath the first nanowire pattern and having a second width wider than the first width.

4. 发明授权

US09570434B2 Semiconductor device and fabricating method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09570434B2
公开(公告)日：2017-02-14
申请号：US15217531
申请日：2016-07-22
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hyun-Jae Kang , Jin-Wook Lee , Kang-Ill Seo , Yong-Min Cho
IPC分类号： H01L27/088 , H01L27/02 , H01L23/522 , H01L21/768 , H01L21/8234
CPC分类号： H01L27/0886 , G03F7/70 , H01L21/0274 , H01L21/32136 , H01L21/32139 , H01L21/76816 , H01L21/76877 , H01L21/76895 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L23/5226 , H01L23/528 , H01L23/53271 , H01L27/0207
摘要： Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first direction, to be spaced apart in a second direction intersecting the first direction, forming first and second gate lines, each extending in the second direction, on the first to fourth fins to be spaced apart in the first direction, forming a first contact on the first gate line between the first and second fins, forming a second contact on the first gate line between the third and fourth fins, forming a third contact on the second gate line between the first and second fins, forming a fourth contact on the second gate line between the third and fourth fins and forming a fifth contact on the first to fourth contacts so as to overlap with the second contact and the third contact and so as not to overlap with the first contact and the fourth contact, wherein the fifth contact is arranged to diagonally traverse a quadrangle defined by the first to fourth contacts.
摘要翻译：提供一种半导体器件及其制造方法。制造方法包括：形成第一至第四鳍片，每个翼片沿第一方向延伸，沿与第一方向相交的第二方向间隔开，形成第一和第二栅极线，每个沿第二方向延伸，第一至第四鳍片在第一方向上间隔开，在第一和第二鳍之间的第一栅极线上形成第一接触，在第三和第四鳍之间的第一栅极线上形成第二接触，在第二栅极线上形成第三接触在第一和第二散热片之间，在第三和第四鳍之间的第二栅极线上形成第四触点，并在第一至第四触点上形成第五触点，以便与第二触点和第三触点重叠，与第一触点和第四触点重叠，其中第五触点布置成对角地横过由第一至第四触点限定的四边形。

5. 发明申请

US20160380084A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20160380084A1
公开(公告)日：2016-12-29
申请号：US15234484
申请日：2016-08-11
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： JONG-HYUK KIM , Kang-Ill Seo , Hyun-Jae Kang , Deok-Han Bae
IPC分类号： H01L29/66 , H01L21/311 , H01L21/308
CPC分类号： H01L29/66795 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/32139
摘要： A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

6. 发明授权

US09905559B2 Semiconductor device having fin-type field effect transistor and method of manufacturing the same 有权
公开(公告)号：US09905559B2
公开(公告)日：2018-02-27
申请号：US15612416
申请日：2017-06-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dong-Il Bae , Kang-Ill Seo
IPC分类号： H01L27/088 , H01L21/31 , H01L29/06 , H01L29/78 , H01L29/161 , H01L29/66 , H01L21/8234 , H01L21/3105 , H01L29/786 , H01L29/775 , H01L29/08 , H01L29/423
CPC分类号： H01L27/0886 , H01L21/31053 , H01L21/823431 , H01L29/0673 , H01L29/0847 , H01L29/161 , H01L29/42364 , H01L29/42392 , H01L29/66439 , H01L29/6681 , H01L29/775 , H01L29/7851 , H01L29/78696
摘要： A semiconductor device includes a first fin structure disposed on a substrate. The first fin structure extends in a first direction. A first sacrificial layer pattern is disposed on the first fin structure. The first sacrificial layer pattern includes a left portion and a right portion arranged in the first direction. A dielectric layer pattern is disposed on the first fin structure and interposed between the left and right portions of the first sacrificial layer pattern. A first active layer pattern extending in the first direction is disposed on the first sacrificial layer pattern and the dielectric layer pattern. A first gate electrode structure is disposed on a portion of the first active layer pattern. The portion of the first active layer is disposed on the dielectric layer pattern. The first gate electrode structure extends in a second direction crossing the first direction.

7. 发明申请

US20170162651A1 SEMICONDUCTOR DEVICE HAVING A GATE ALL AROUND STRUCTURE AND A METHOD FOR FABRICATING THE SAME 有权
公开(公告)号：US20170162651A1
公开(公告)日：2017-06-08
申请号：US14961213
申请日：2015-12-07
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： SUNG-DAE SUK , Bom-Soo Kim , Kang-Ill Seo
IPC分类号： H01L29/06 , H01L27/12 , H01L29/51 , H01L29/417 , H01L29/423 , H01L29/78
CPC分类号： H01L29/0673 , H01L27/1211 , H01L29/41775 , H01L29/42392 , H01L29/511 , H01L29/66439 , H01L29/785
摘要： A semiconductor device includes a wire pattern spaced apart from a substrate and extended in a first direction, a gate electrode disposed around a circumference of the wire pattern and extended in a second direction that is different from the first direction, a source disposed on a first side of the gate electrode, a drain disposed on a second side of the gate electrode, the source and the drain connected to the wire pattern and a gate spacer disposed on first and second sidewalls of the gate electrode, on the source and on the drain.

8. 发明授权

US09601569B1 Semiconductor device having a gate all around structure 有权
公开(公告)号：US09601569B1
公开(公告)日：2017-03-21
申请号：US14961378
申请日：2015-12-07
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sung-Dae Suk , Kang-Ill Seo
IPC分类号： H01L29/06 , H01L29/78 , H01L29/423 , H01L29/08 , H01L27/12
CPC分类号： H01L29/0673 , B82Y10/00 , H01L27/1211 , H01L29/0847 , H01L29/42392 , H01L29/66439 , H01L29/785
摘要： A semiconductor includes a substrate including a first region and a second region, a fin extending in a first direction in the first region of the substrate, wherein the fin includes a first semiconductor pattern and a second semiconductor pattern that are disposed on each other, a first wire pattern extending in a second direction in the second region of the substrate, a first gate electrode disposed on the fin, wherein the first gate electrode extends in a third direction that is different from the first direction, and a second gate electrode surrounding an outer perimeter of the first wire pattern and extending in a fourth direction that is different from the second direction.

9. 发明授权

US09425259B1 Semiconductor device having a fin 有权
标题翻译：具有翅片的半导体器件
公开(公告)号：US09425259B1
公开(公告)日：2016-08-23
申请号：US14802898
申请日：2015-07-17
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sung-Dae Suk , Kang-Ill Seo
IPC分类号： H01L29/78 , H01L29/10 , H01L29/165 , H01L29/08 , H01L29/06
CPC分类号： H01L29/1054 , H01L29/0653 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/7851 , H01L29/78696
摘要： Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region.
摘要翻译：提供一种半导体器件。半导体器件包括沿第一方向设置在衬底上的翅片。牺牲层设置在翅片上。有源层设置在牺牲层上。沿着与第一方向相交的第二方向设置栅极绝缘层和栅电极。栅极绝缘层覆盖有源层的大致整个顶部，侧面和底部表面。源极或漏极区域设置在衬底上的栅电极的至少一侧上。在第一区域和第二区域中的第一区域和第二区域中的锗的第一浓度高于设置在第一区域和第二区域之间的第三区域中的第二浓度的锗。

10. 发明授权

US09397179B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09397179B1
公开(公告)日：2016-07-19
申请号：US14624098
申请日：2015-02-17
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kang-Ill Seo
IPC分类号： H01L27/088 , H01L29/423 , H01L29/06 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0669 , H01L29/41733 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A semiconductor device including an active region having a field insulating layer disposed at a first side thereof; a first wire pattern formed on the active region and extended in a first direction; a normal gate formed on the active region, extended in a second direction crossing the first direction and covering the first wire pattern; and a dummy gate having a first part which overlaps a first end of the field insulating layer and a second part which overlaps the active region, and wherein the dummy gate is formed on the active region and spaced apart from the normal gate in the first direction, wherein the first wire pattern penetrates a third part of the dummy gate and the dummy gate covers a first end of the first wire pattern.
摘要翻译：一种半导体器件，包括具有设置在其第一侧的场绝缘层的有源区; 形成在所述有源区上并沿第一方向延伸的第一布线图案; 形成在所述有源区上的正常栅极，沿与所述第一方向交叉的第二方向延伸并覆盖所述第一布线图案; 以及具有与所述场绝缘层的第一端重叠的第一部分的虚拟栅极和与所述有源区域重叠的第二部分，并且其中所述伪栅极形成在所述有源区上并且沿所述第一方向与所述正常栅极间隔开，其中所述第一布线图案穿透所述伪栅极的第三部分，并且所述伪栅极覆盖所述第一布线图案的第一端。

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