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1. 发明申请

US20220101894A1 MEMORY DEVICE INCLUDING MULTIPLE MEMORY CHIPS AND DATA SIGNAL LINES AND A METHOD OF OPERATING THE MEMORY DEVICE 有权
公开(公告)号：US20220101894A1
公开(公告)日：2022-03-31
申请号：US17410210
申请日：2021-08-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Seonkyoo Lee , Chiweon Yoon , Byunghoon Jeong , Youngmin Jo
IPC分类号： G11C7/10 , H01L25/065
摘要： An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

2. 发明授权

US11567879B2 Method of encrypting data in nonvolatile memory device, nonvolatile memory device and user device 有权
公开(公告)号：US11567879B2
公开(公告)日：2023-01-31
申请号：US17118091
申请日：2020-12-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Youngmin Jo , Daeseok Byeon , Kisung Kim
IPC分类号： G06F12/14 , G06F21/72 , G06F21/79 , G06F21/85 , H04L9/06 , G06F21/74
摘要： A method of encrypting data in a nonvolatile memory device (NVM) includes; programming data in selected memory cells, sensing the selected memory cells at a first time during a develop period to provide random data, sensing the selected memory cells at a second time during the develop period to provide main data, encrypting the main data using the random data to generate encrypted main data, and outputting the encrypted main data to an external circuit, wherein the randomness of the random data is based on a threshold voltage distribution of the selected memory cells.

3. 发明授权

US11157425B2 Memory device, memory system including memory device and vehicle-based system including memory system 有权
公开(公告)号：US11157425B2
公开(公告)日：2021-10-26
申请号：US16853807
申请日：2020-04-21
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Youngmin Jo , Daeseok Byeon , Tongsung Kim
IPC分类号： G06F13/16 , G06N3/04 , H01L25/065 , H01L25/18
摘要： A memory device provides a first memory area and a second memory area. A smart buffer includes; a priority setting unit receiving sensing data and a corresponding weight, determining a priority of the sensing data based on the corresponding weight, and classifying the sensing data as first priority sensing data or second priority sensing data based on the priority, and a channel controller allocating a channel to a first channel group, allocating another channel to a second channel group, assigning the first channel group to process the first priority sensing data in relation to the first memory area, and assigning the second channel group to process the second priority sensing data in relation to the second memory area.

4. 发明授权

US11594287B2 Nonvolatile memory device and storage device including the nonvolatile memory device 有权
公开(公告)号：US11594287B2
公开(公告)日：2023-02-28
申请号：US17198382
申请日：2021-03-11
申请人： Samsung Electronics Co., Ltd.
发明人： Tongsung Kim , Youngmin Jo , Chiweon Yoon
IPC分类号： G11C16/32 , G11C16/04 , H01L25/065
摘要： A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

5. 发明授权

US11289150B2 Memory system and operating method of the same 有权
公开(公告)号：US11289150B2
公开(公告)日：2022-03-29
申请号：US17196183
申请日：2021-03-09
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Youngmin Jo , Taehyo Kim , Daeseok Byeon , Seungwon Lee
IPC分类号： G11C11/40 , G11C11/4072 , G11C5/06 , G11C11/4093 , G11C11/4099
摘要： A memory system is provided. The memory system includes a memory device having a plurality of memory cells; and a memory controller configured to control the memory device to: store write data in first memory cells from among the plurality of memory cells, identify a current charge amount of a first cell string including at least one of the first memory cells and a current charge amount of a second cell string adjacent to the first cell string, and store dummy data in at least one memory cell connected to the first cell string or the second cell string based on the current charge amount of the first cell string and the current charge amount of the second cell string.

6. 发明授权

US11115021B2 Impedance calibration circuit and memory device including the same 有权
公开(公告)号：US11115021B2
公开(公告)日：2021-09-07
申请号：US17021728
申请日：2020-09-15
申请人： Samsung Electronics Co., Ltd.
发明人： Tongsung Kim , Youngmin Jo , Jungjune Park , Jindo Byun , Dongho Shin , Jeongdon Ihm
IPC分类号： H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
摘要： An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

7. 发明授权

US11502687B2 Impedance calibration circuit and memory device including the same 有权
公开(公告)号：US11502687B2
公开(公告)日：2022-11-15
申请号：US17389148
申请日：2021-07-29
申请人： Samsung Electronics Co., Ltd.
发明人： Tongsung Kim , Youngmin Jo , Jungjune Park , Jindo Byun , Dongho Shin , Jeongdon Ihm
IPC分类号： H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
摘要： An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

8. 发明授权

US11309033B2 Memory device 有权
公开(公告)号：US11309033B2
公开(公告)日：2022-04-19
申请号：US17121015
申请日：2020-12-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Taehyo Kim , Daeseok Byeon , Youngmin Jo , Seungwon Lee
IPC分类号： G11C16/22 , G11C16/04 , G11C16/10 , G11C16/26 , H01L27/11556 , H01L27/11529 , H01L27/11573 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11582
摘要： A memory device including: a memory area having a first memory block and a second memory block; and a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable, wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.

9. 发明授权

US11163453B2 Memory device, memory system including memory device and vehicle-based system including memory system 有权
公开(公告)号：US11163453B2
公开(公告)日：2021-11-02
申请号：US17027978
申请日：2020-09-22
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Youngmin Jo , Daeseok Byeon , Tongsung Kim
IPC分类号： G06F3/06 , G06N3/08 , G06F12/02
摘要： A memory device comprises a smart buffer, and a memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive a sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data as one of first priority sensing data and second priority sensing data, and a channel controller configured to allocate at least one channel selected from among a plurality of channels to a first channel group, allocate at least another channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sensing data in relation to the first memory area, and assign the second channel group to process the second priority sensing data in relation to the second memory area, wherein a number of data input/output (I/O) pins connected to the first channel group is greater than a number of data I/O pins connected to the second channel group, wherein the memory area includes at least one memory chip, wherein the at least one memory chip includes a first chip having a first metal pad and a cell region and a second chip having a second metal pad and a peripheral circuit region, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

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