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1. 发明授权

US09576660B2 Low forming voltage non-volatile storage device 有权
标题翻译：低成型电压非易失性存储装置
公开(公告)号：US09576660B2
公开(公告)日：2017-02-21
申请号：US14996144
申请日：2016-01-14
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流被限制。在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。

2. 发明授权

US08861258B2 Set/reset algorithm which detects and repairs weak cells in resistive-switching memory device 有权
标题翻译：设置/复位算法，用于检测和修复电阻式切换存储器件中的弱电池
公开(公告)号：US08861258B2
公开(公告)日：2014-10-14
申请号：US13772729
申请日：2013-02-21
申请人： SanDisk 3D LLC
发明人： Zhida Lan , Roy E Scheuerlein , Thomas Yan
IPC分类号： G11C13/00 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0002 , G11C13/0064 , G11C29/4401 , G11C29/50008 , G11C2013/0073 , G11C2029/5002
摘要： A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.
摘要翻译：电阻切换存储单元在设置或复位操作中被编程，该操作测试单元的稳定性。使用程序电压的第一个编程阶段，在程序验证测试通过之前，幅度或持续时间会增加。然后执行稳定性测试阶段以评估存储器单元的稳定性。稳定性测试阶段通过施加一个或多个干扰脉冲并执行一个或多个稳定性验证测试来确定存储器单元是否弱并且可能转移到设置或复位状态之外。与编程电压相比，干扰脉冲可以具有减小的幅度或持续时间。如果稳定性测试阶段指示存储单元不稳定，则执行第二编程阶段。如果稳定性测试阶段表明存储单元稳定，则操作结束。

3. 发明授权

US09704920B2 Resistive random access memory containing a steering element and a tunneling dielectric element 有权
公开(公告)号：US09704920B2
公开(公告)日：2017-07-11
申请号：US14924144
申请日：2015-10-27
申请人： SANDISK 3D LLC
发明人： Abhijit Bandyopadhyay , Venkatagirish Nagavarapu , Xiao Li , Zhida Lan , Michael Konevecki
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/12 , H01L45/1226 , H01L45/146 , H01L45/1608 , H01L45/1666
摘要： A memory device includes at least one memory cell. The at least one memory cell includes a steering element, a resistive memory element, and a tunneling dielectric element located between the steering element and the resistive memory element.

4. 发明授权

US09472758B2 High endurance non-volatile storage 有权
标题翻译：高耐久性非易失性存储
公开(公告)号：US09472758B2
公开(公告)日：2016-10-18
申请号：US14538763
申请日：2014-11-11
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Abhijit Bandyopadhyay , Christopher Petti , Li Xiao , Girish Nagavarapu
IPC分类号： G11C5/02 , H01L45/00 , G11C13/00 , H01L27/24
CPC分类号： H01L45/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2013/0083 , G11C2013/0092 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/146 , H01L45/1683
摘要： The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.
摘要翻译：非易失性存储系统的制造包括为非易失性存储元件沉积一层或多层可逆电阻切换材料。在操作之前，在制造期间或之后，进行成形操作。在一个实施例中，形成操作包括向一个或多个可逆电阻切换材料层施加成形电压以形成包括电阻器的第一区域和可在低电流下可逆地改变电阻的第二区域，电阻器响应于成形条件而形成，并且不会沉积在该装置上。在一些实施例中，对非易失性存储元件的编程包括施加在低电流下随时间增加的电压但不超过最终形成电压的编程电压。

5. 发明申请

US20140233299A1 Set/Reset Algorithm Which Detects And Repairs Weak Cells In Resistive-Switching Memory Device 有权
标题翻译：在电阻式切换存储器件中检测和修复弱电池的设置/复位算法
公开(公告)号：US20140233299A1
公开(公告)日：2014-08-21
申请号：US13772729
申请日：2013-02-21
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Thomas Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0002 , G11C13/0064 , G11C29/4401 , G11C29/50008 , G11C2013/0073 , G11C2029/5002
摘要： A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability of the memory cell. The stability test phase determines whether the memory cell is weak and likely to transition out of the set or reset state by applying one or more disturb pulses and performing one or more stability verify tests. The disturb pulses can have a reduced magnitude or duration compared to the program voltages. If the stability test phase indicates the memory cell is not stable, a second programming phase is performed. If the stability test phase indicates the memory cell is stable, the operation is concluded.
摘要翻译：电阻切换存储单元在设置或复位操作中被编程，该操作测试单元的稳定性。使用程序电压的第一个编程阶段，在程序验证测试通过之前，幅度或持续时间会增加。然后执行稳定性测试阶段以评估存储器单元的稳定性。稳定性测试阶段通过施加一个或多个干扰脉冲并执行一个或多个稳定性验证测试来确定存储器单元是否弱并且可能转移到设置或复位状态之外。与编程电压相比，干扰脉冲可以具有减小的幅度或持续时间。如果稳定性测试阶段指示存储单元不稳定，则执行第二编程阶段。如果稳定性测试阶段表明存储单元稳定，则操作结束。

6. 发明申请

US20130170283A1 LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE 有权
标题翻译：低成型电压非易失存储器件
公开(公告)号：US20130170283A1
公开(公告)日：2013-07-04
申请号：US13709349
申请日：2012-12-10
申请人： Sandisk 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储元件设置在跨越半导体衬底的不同距离上的多个平面中。所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。在具有极性的成形期间，将形成电压施加到存储元件，使得位线用作阴极，并且字线用作阳极，阴极与开关材料相比具有较低的电子注入能量势垒。

7. 发明申请

US20160133836A1 HIGH ENDURANCE NON-VOLATILE STORAGE 有权
标题翻译：高耐久性非挥发性储存
公开(公告)号：US20160133836A1
公开(公告)日：2016-05-12
申请号：US14538763
申请日：2014-11-11
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Abhijit Bandyopadhyay , Christopher Petti , Li Xiao , Girish Nagavarapu
IPC分类号： H01L45/00 , H01L27/24 , G11C13/00
CPC分类号： H01L45/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2013/0083 , G11C2013/0092 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/146 , H01L45/1683
摘要： The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.
摘要翻译：非易失性存储系统的制造包括为非易失性存储元件沉积一层或多层可逆电阻切换材料。在操作之前，在制造期间或之后，进行成形操作。在一个实施例中，形成操作包括向一个或多个可逆电阻切换材料层施加成形电压以形成包括电阻器的第一区域和可在低电流下可逆地改变电阻的第二区域，电阻器响应于成形条件而形成，并且不会沉积在该装置上。在一些实施例中，对非易失性存储元件的编程包括施加在低电流下随时间增加的电压但不超过最终形成电压的编程电压。

8. 发明申请

US20160133325A1 LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE 有权
标题翻译：低成型电压非易失存储器件
公开(公告)号：US20160133325A1
公开(公告)日：2016-05-12
申请号：US14996144
申请日：2016-01-14
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。

9. 发明授权

US09269425B2 Low forming voltage non-volatile storage device 有权
标题翻译：低成型电压非易失性存储装置
公开(公告)号：US09269425B2
公开(公告)日：2016-02-23
申请号：US13709349
申请日：2012-12-10
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。

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