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1. 发明授权

US09698153B2 Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad 有权
公开(公告)号：US09698153B2
公开(公告)日：2017-07-04
申请号：US15080269
申请日：2016-03-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jin Liu , Yanli Zhang , Murshed Chowdhury , Raghuveer S. Makala , Johann Alsmeier
IPC分类号： H01L27/00 , H01L27/1157 , H01L27/11582 , H01L21/28 , H01L21/822 , H01L27/11551 , H01L27/06 , H01L27/11524 , H01L27/11578 , H01L29/66 , H01L29/788 , H01L29/792 , H01L27/11556
CPC分类号： H01L27/1157 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2224/32145
摘要： Alignment between memory openings through multiple tier structures can be facilitated employing a temporary landing pad. The temporary landing pad can have a greater area than the horizontal cross-sectional area of a first memory opening through a first tier structure including a first alternating stack of first insulating layers and first spacer material layers. An upper portion of a first memory film is removed, and a sidewall of an insulating cap layer that defines the first memory opening can be laterally recessed to form a recessed cavity. A sacrificial fill material is deposited in the recessed cavity to form a sacrificial fill material portion, which functions as the temporary landing pad for a second memory opening that is subsequently formed through a second tier structure including second insulating layers and second spacer material layers. A memory stack structure can be formed through the first and second tier structures.

2. 发明授权

US09576975B2 Monolithic three-dimensional NAND strings and methods of fabrication thereof 有权
标题翻译：单片三维NAND串及其制造方法
公开(公告)号：US09576975B2
公开(公告)日：2017-02-21
申请号：US14957762
申请日：2015-12-03
申请人： SANDISK TECHNOLOGIES, INC.
发明人： Yanli Zhang , James Kai , Raghuveer S. Makala , Jin Liu , Murshed Chowdhury , Camilla Huang , Johann Alsmeier
IPC分类号： H01L27/115 , H01L21/768
CPC分类号： H01L27/11582 , H01L21/7682 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
摘要： A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide material layer, a first silicon oxide material layer, and an upper silicon oxide material layer. A memory opening can be formed through the vertically repeating stack, and a layer stack including a blocking dielectric layer, a memory material layer, a tunneling dielectric, and a semiconductor channel can be formed in the memory opening. The sacrificial material layers are replaced with electrically conductive layers. The first silicon oxide material layer can be removed to form backside recesses. Optionally, portions of the memory material layer can be removed to from discrete charge storage regions. The backside recesses can be filled with a low-k dielectric material and/or can include cavities within a dielectric material to provide reduced coupling between electrically conductive layers.
摘要翻译：在衬底上形成单位层堆叠的垂直重复堆叠。单位层堆叠包括牺牲材料层，下部氧化硅材料层，第一氧化硅材料层和上部氧化硅材料层。可以通过垂直重复堆叠形成存储器开口，并且可以在存储器开口中形成包括阻挡介电层，存储材料层，隧道电介质和半导体沟道的层堆叠。牺牲材料层被导电层代替。可以去除第一氧化硅材料层以形成背面凹槽。可选地，存储材料层的部分可以从离散的电荷存储区域移除。背面凹槽可以填充低k电介质材料和/或可以包括电介质材料内的空腔以提供导电层之间的减小的耦合。

3. 发明申请

US20170278571A1 THREE DIMENSIONAL NAND MEMORY DEVICE WITH COMMON BIT LINE FOR MULTIPLE NAND STRINGS IN EACH MEMORY BLOCK 审中-公开
公开(公告)号：US20170278571A1
公开(公告)日：2017-09-28
申请号：US15078555
申请日：2016-03-23
申请人： SANDISK TECHNOLOGIES INC.
发明人： Murshed Chowdhury , Jin Liu , Yanli Zhang , Andrew Lin , Raghuveer S. Makala , Johann Alsmeier
IPC分类号： G11C16/04 , G11C16/26 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.

4. 发明授权

US09530791B1 Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same 有权
公开(公告)号：US09530791B1
公开(公告)日：2016-12-27
申请号：US14883966
申请日：2015-10-15
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yanli Zhang , Raghuveer S. Makala , Jin Liu , Murshed Chowdhury , Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L27/115
摘要： A three-dimensional memory device including multiple stack structures can be formed with a joint region electrode, which is an electrode formed at a joint region located near the interface between an upper stack structure and a lower stack structure. A memory stack structure is formed through the multiple stack structures. The joint region electrode laterally surrounds a portion of the memory stack structure in proximity to the interface between different stack structures. The joint region electrode includes a layer portion having a thickness and a collar portion that laterally surrounds the memory stack structure and having a greater vertical extent than the thickness of the layer portion. The increased vertical extent of the collar portion with respect to the vertical extent of the layer portion provides enhanced control of a portion of a semiconductor channel in the memory stack structure located near the interface between different stack structures.

5. 发明授权

US09397111B1 Select gate transistor with single crystal silicon for three-dimensional memory 有权
标题翻译：选择具有单晶硅的栅极晶体管用于三维存储器
公开(公告)号：US09397111B1
公开(公告)日：2016-07-19
申请号：US14927828
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Murshed Chowdhury , Yanli Zhang , Jin Liu , Raghuveer S Makala , Johann Alsmeier
IPC分类号： H01L27/115 , H01L21/02
CPC分类号： H01L27/1157 , H01L21/02532 , H01L21/02675 , H01L21/28282 , H01L27/11582
摘要： A fabrication process for a 3D memory structure provides a single crystal silicon channel for a drain-side select gate (SGD) transistor using a laser thermal anneal (LTA). The 3D memory structure includes a stack formed from an array of alternating conductive and dielectric layers. A NAND string is formed by filling a memory hole with memory films, including a charge trapping material, a tunnel oxide and a polysilicon channel. In one case, a separate oxide and polysilicon forms the SGD transistor gate oxide and channel respectively, where LTA is performed on the polysilicon. In another case, the same oxide and polysilicon are used for the SGD transistor and the memory cells. A portion of the polysilicon is converted to single crystal silicon. A back side of the single crystal silicon is subject to epitaxial growth and thermal oxidation via a void in a control gate layer.
摘要翻译：用于3D存储器结构的制造工艺为使用激光热退火（LTA）的漏极侧选择栅极（SGD）晶体管提供单晶硅沟道。 3D存储器结构包括由交替导电和电介质层的阵列形成的堆叠。通过用包括电荷捕获材料，隧道氧化物和多晶硅沟道的存储膜填充存储器孔来形成NAND串。在一种情况下，单独的氧化物和多晶硅分别形成SGD晶体管栅极氧化物和沟道，其中在多晶硅上执行LTA。在另一种情况下，相同的氧化物和多晶硅用于SGD晶体管和存储单元。多晶硅的一部分被转换为单晶硅。单晶硅的背面通过控制栅极层中的空隙进行外延生长和热氧化。

6. 发明授权

US10224104B2 Three dimensional NAND memory device with common bit line for multiple NAND strings in each memory block 有权
公开(公告)号：US10224104B2
公开(公告)日：2019-03-05
申请号：US15078555
申请日：2016-03-23
申请人： SANDISK TECHNOLOGIES INC.
发明人： Murshed Chowdhury , Jin Liu , Yanli Zhang , Andrew Lin , Raghuveer S. Makala , Johann Alsmeier
IPC分类号： G11C16/10 , G11C16/26 , G11C16/04 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.

7. 发明授权

US09570463B1 Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same 有权
标题翻译：具有具有套环部分的接合电极的多层存储器堆叠结构及其制造方法
公开(公告)号：US09570463B1
公开(公告)日：2017-02-14
申请号：US14883966
申请日：2015-10-15
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yanli Zhang , Raghuveer S. Makala , Jin Liu , Murshed Chowdhury , Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A three-dimensional memory device including multiple stack structures can be formed with a joint region electrode, which is an electrode formed at a joint region located near the interface between an upper stack structure and a lower stack structure. A memory stack structure is formed through the multiple stack structures. The joint region electrode laterally surrounds a portion of the memory stack structure in proximity to the interface between different stack structures. The joint region electrode includes a layer portion having a thickness and a collar portion that laterally surrounds the memory stack structure and having a greater vertical extent than the thickness of the layer portion. The increased vertical extent of the collar portion with respect to the vertical extent of the layer portion provides enhanced control of a portion of a semiconductor channel in the memory stack structure located near the interface between different stack structures.
摘要翻译：包括多个堆叠结构的三维存储器件可以形成有接合区域电极，该接合区域电极是形成在位于上部堆叠结构和下部堆叠结构之间的界面附近的接合区域处的电极。通过多个堆叠结构形成存储器堆叠结构。接合区域电极在不同的堆叠结构之间的界面附近横向地围绕存储器堆叠结构的一部分。接合区域电极包括具有厚度的层部分和环形部分，该部分横向包围存储器堆叠结构并且具有比层部分的厚度更大的垂直范围。套环部分相对于层部分的垂直范围增加的垂直范围提供对位于不同堆叠结构之间的界面附近的存储器堆叠结构中的半导体通道的一部分的增强的控制。

8. 发明申请

US20160204117A1 VERTICAL NAND AND METHOD OF MAKING THEREOF USING SEQUENTIAL STACK ETCHING AND SELF-ALIGNED LANDING PAD 有权
标题翻译：垂直NAND及其使用顺序堆叠蚀刻和自对准着陆垫制作的方法
公开(公告)号：US20160204117A1
公开(公告)日：2016-07-14
申请号：US15080269
申请日：2016-03-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jin Liu , Yanli Zhang , Murshed Chowdhury , Raghuveer S. Makala , Johann Alsmeier
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L27/1157 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2224/32145
摘要： Alignment between memory openings through multiple tier structures can be facilitated employing a temporary landing pad. The temporary landing pad can have a greater area than the horizontal cross-sectional area of a first memory opening through a first tier structure including a first alternating stack of first insulating layers and first spacer material layers. An upper portion of a first memory film is removed, and a sidewall of an insulating cap layer that defines the first memory opening can be laterally recessed to form a recessed cavity. A sacrificial fill material is deposited in the recessed cavity to form a sacrificial fill material portion, which functions as the temporary landing pad for a second memory opening that is subsequently formed through a second tier structure including second insulating layers and second spacer material layers. A memory stack structure can be formed through the first and second tier structures.
摘要翻译：通过多个层结构的存储器开口之间的对准可以利用临时着陆焊盘来进行。临时着陆垫可以具有比通过包括第一绝缘层和第一间隔材料层的第一交替堆叠的第一层结构的第一存储器开口的水平横截面积更大的面积。去除第一存储膜的上部，并且限定第一存储器开口的绝缘盖层的侧壁可以被横向凹入以形成凹腔。牺牲填充材料沉积在凹腔中以形成牺牲填充材料部分，其用作第二存储器开口的临时着陆焊盘，其随后通过包括第二绝缘层和第二间隔材料层的第二层结构形成。可以通过第一和第二层结构形成存储器堆叠结构。

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