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1. 发明授权

US09576966B1 Cobalt-containing conductive layers for control gate electrodes in a memory structure 有权
标题翻译：用于存储器结构中的控制栅电极的含钴导电层
公开(公告)号：US09576966B1
公开(公告)日：2017-02-21
申请号：US14859710
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： Somesh Peri , Raghuveer S. Makala , Sateesh Koka , Rahul Sharangpani
IPC分类号： H01L27/115 , H01L27/02 , H01L21/283 , H01L21/324
CPC分类号： H01L27/115 , H01L21/283 , H01L27/0207 , H01L27/1157 , H01L27/11582
摘要： An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers from the backside trench selective to the insulating layers. A cobalt-containing material is deposited such that the cobalt-containing material continuously extends at least between a neighboring pair of cobalt-containing material portions in respective backside recesses. An anneal is performed at an elevated temperature to migrate vertically-extending portions of the cobalt-containing material into the backside recesses, thereby forming vertically separated cobalt-containing material portions confined within the backside recesses. Sidewalls of the insulating layers may be rounded or tapered to facilitate migration of the cobalt-containing material.
摘要翻译：绝缘层和牺牲材料层的交替堆叠可以形成在衬底上。通过交替堆叠形成存储器堆叠结构和背面沟槽。通过从对绝缘层选择性的背面沟槽去除牺牲材料层而形成背面凹部。沉积含钴材料，使得含钴材料至少在相应的背面凹槽中的相邻的一对含钴材料部分之间连续延伸。在升高的温度下进行退火以将含钴材料的垂直延伸部分迁移到背面凹槽中，从而形成限制在背面凹槽内的垂直分离的含钴材料部分。绝缘层的侧壁可以是圆形或锥形以促进含钴材料的迁移。

2. 发明授权

US09496419B2 Ruthenium nucleation layer for control gate electrodes in a memory structure 有权
标题翻译：钌成核层，用于存储结构中的控制栅电极
公开(公告)号：US09496419B2
公开(公告)日：2016-11-15
申请号：US14553124
申请日：2014-11-25
申请人： SanDisk Technologies, Inc.
发明人： Rahul Sharangpani , Raghuveer S. Makala , Sateesh Koka , George Matamis
IPC分类号： H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7889 , H01L27/11519 , H01L27/11531 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/7926
摘要： A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a ruthenium portion can be formed in each backside recess, and a polycrystalline conductive material portion can be formed on each ruthenium portion. Each ruthenium portion can be employed in lieu of a tungsten seed layer to function as a lower resistivity seed layer that enables subsequent deposition of a polycrystalline conductive material. The resulting electrically conductive lines can have a lower resistivity than conductive lines of comparable dimensions that employ tungsten seed layers.
摘要翻译：可以在每个存储器开口内形成记忆膜和半导体通道，该存储器开口延伸穿过包括交替的多个绝缘体层和牺牲材料层的堆叠。在通过去除对绝缘体层选择性的牺牲材料层形成后侧凹槽之后，可以在每个后侧凹部中形成钌部分，并且可以在每个钌部分上形成多晶导电材料部分。可以使用每个钌部分代替钨种子层，以用作能够随后沉积多晶导电材料的较低电阻率种子层。所得到的导电线可以具有比使用钨种子层的相当尺寸的导线更低的电阻率。

3. 发明申请

US20160211272A1 SEMICONDUCTOR STRUCTURE WITH CONCAVE BLOCKING DIELECTRIC SIDEWALL AND METHOD OF MAKING THEREOF BY ISOTROPICALLY ETCHING THE BLOCKING DIELECTRIC LAYER 有权
标题翻译：具有嵌入式电介质面板的半导体结构及其通过等离子体蚀刻阻塞介质层制造的方法
公开(公告)号：US20160211272A1
公开(公告)日：2016-07-21
申请号：US14600226
申请日：2015-01-20
申请人： SANDISK TECHNOLOGIES INC.
发明人： Sateesh Koka , Senaka Kanakamedala , Raghuveer S. Makala , Rahul Sharangpani , Yanli Zhang , Yao-Sheng Lee , George Matamis
IPC分类号： H01L27/115 , H01L29/66 , H01L21/311 , H01L21/28 , H01L29/788
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/6653 , H01L29/7883
摘要： A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched by an isotropic etch process that minimizes overetch into the substrate. An optional additional blocking dielectric layer, at least one charge storage element, a tunneling dielectric, and a semiconductor channel can be sequentially formed in the memory opening to provide a three-dimensional memory stack.
摘要翻译：第一隔离介电层通过交替的多个材料层和绝缘体层的堆叠形成在存储器开口中。具有底部开口的间隔物通过沉积保形材料层和各向异性蚀刻形成在第一阻挡介电层上。存储器开口底部的第一阻挡介质层的水平部分可以通过各向同性的蚀刻工艺进行蚀刻，该过程使过蚀刻最小化到衬底中。可以在存储器开口中顺序地形成可选的附加阻挡介质层，至少一个电荷存储元件，隧道电介质和半导体沟道，以提供三维存储堆叠。

4. 发明授权

US09397046B1 Fluorine-free word lines for three-dimensional memory devices 有权
标题翻译：无氟字线用于三维存储器件
公开(公告)号：US09397046B1
公开(公告)日：2016-07-19
申请号：US14699749
申请日：2015-04-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Rahul Sharangpani , Raghuveer S. Makala , Sateesh Koka , George Matamis
IPC分类号： H01L29/76 , H01L23/532 , H01L27/115 , H01L23/535 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76877 , H01L23/53257 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Fluorine-induced formation of voids and electrical shorts can be avoided by forming fluorine-free metal lines. Specifically, control gate electrodes of a three-dimensional memory device can be formed employing fluorine-free deposition processes. Fluorine-free tungsten nitride can be deposited as a metallic barrier liner employing atomic layer deposition. Fluorine-free tungsten nucleation layer can be subsequently deposited. Fluorine-free tungsten fill process can be employed to form the control gate electrodes. The fluorine-free control gate electrodes do not include fluorine therein, and thus, circumvents yield and reliability issues associated with residual fluorine that are present in fluorine-containing metal lines.
摘要翻译：通过形成无氟金属线可以避免氟引起的空隙形成和电短路。具体地，可以使用无氟沉积工艺形成三维存储器件的控制栅电极。可以使用原子层沉积作为金属阻挡层而沉积无氟氮化钨。随后可以沉积无氟钨成核层。可以使用无氟钨填充工艺来形成控制栅电极。无氟控制栅电极中不含氟，因此，避免了存在于含氟金属线中的残留氟的产率和可靠性问题。

5. 发明授权

US10128261B2 Cobalt-containing conductive layers for control gate electrodes in a memory structure 有权
公开(公告)号：US10128261B2
公开(公告)日：2018-11-13
申请号：US14613956
申请日：2015-02-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： Raghuveer S. Makala , Rahul Sharangpani , Sateesh Koka , Genta Mizuno , Naoki Takeguchi , Senaka Krishna Kanakamedala , George Matamis , Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11556 , H01L29/49 , H01L21/28 , H01L27/11563 , H01L27/11578 , H01L29/66 , H01L29/788 , H01L29/792 , H01L21/3213 , H01L21/768 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11568
摘要： A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.

6. 发明授权

US09842907B2 Memory device containing cobalt silicide control gate electrodes and method of making thereof 有权
公开(公告)号：US09842907B2
公开(公告)日：2017-12-12
申请号：US14869406
申请日：2015-09-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Raghuveer S. Makala , Sateesh Koka , Zhenyu Lu , Somesh Peri , Rahul Sharangpani
IPC分类号： H01L21/8239 , H01L29/49 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/788 , H01L21/28 , H01L21/285 , H01L27/11568
CPC分类号： H01L29/4975 , H01L21/28273 , H01L21/28282 , H01L21/28518 , H01L27/11524 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/7883
摘要： An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers from the backside trench selective to the insulating layers. A cobalt-semiconductor alloy portion is formed in each backside recess by reacting cobalt and a semiconductor material. Conductive material in the backside trench can be removed by an etch to electrically isolate cobalt-containing alloy portions located in different backside recesses. Electrically conductive layers including a respective cobalt-semiconductor alloy portion can be employed as word lines of a three-dimensional memory device.

7. 发明授权

US09515079B2 Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack 有权
标题翻译：具有阻塞电介质的三维存储器件具有增强的防止氟侵蚀的保护
公开(公告)号：US09515079B2
公开(公告)日：2016-12-06
申请号：US14751922
申请日：2015-06-26
申请人： SanDisk Technologies, Inc.
发明人： Sateesh Koka , Raghuveer S. Makala , Somesh Peri , Rahul Sharangpani , Yao-Sheng Lee , George Matamis , Wei Zhao
IPC分类号： H01L27/115 , H01L21/223 , H01L21/02 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L21/02164 , H01L21/02178 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/02356 , H01L21/2236 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/7883 , H01L29/792
摘要： Blocking dielectric structures and/or thicker barrier metal films for preventing or reducing fluorine diffusion are provided. A blocking dielectric layer can be formed as an outer layer of a memory film in a memory stack structure extending through electrically insulating layers and sacrificial material layers. After formation of backside recesses by removal of the sacrificial material layers, dopants can be introduced into physically exposed portions of the blocking dielectric layer, for example, by plasma treatment or thermal treatment, to form silicon oxynitride regions which can reduce or prevent fluorine diffusion. Alternatively or additionally, a set of metal oxide blocking dielectric material portions can be formed in the backside recesses to retard or prevent fluorine diffusion. To minimize adverse impact on the electrically conductive layers formed in the backside recesses, the blocking dielectric material portions can be laterally recessed from a trench employed to form the backside recesses.
摘要翻译：提供了用于阻止或减少氟扩散的阻挡电介质结构和/或较厚的阻挡金属膜。可以在延伸穿过电绝缘层和牺牲材料层的存储器堆叠结构中形成隔离电介质层作为存储膜的外层。在通过去除牺牲材料层形成背面凹槽之后，可以例如通过等离子体处理或热处理将掺杂剂引入到阻挡介电层的物理暴露部分中，以形成可以减少或防止氟扩散的氮氧化硅区域。或者或另外，可以在背面凹部中形成一组金属氧化物阻挡介电材料部分，以延迟或防止氟扩散。为了最小化对形成在背面凹槽中的导电层的不利影响，阻挡电介质材料部分可以从用于形成背面凹槽的沟槽侧向凹入。

8. 发明授权

US09478558B2 Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer 有权
标题翻译：具有凹陷电介质侧壁的半导体结构及其通过各向同性蚀刻阻挡介电层来制造的方法
公开(公告)号：US09478558B2
公开(公告)日：2016-10-25
申请号：US14600226
申请日：2015-01-20
申请人： SANDISK TECHNOLOGIES INC.
发明人： Sateesh Koka , Senaka Kanakamedala , Raghuveer S. Makala , Rahul Sharangpani , Yanli Zhang , Yao-Sheng Lee , George Matamis
IPC分类号： H01L21/8238 , H01L27/115 , H01L21/28 , H01L29/788 , H01L21/311 , H01L29/66
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/6653 , H01L29/7883
摘要： A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched by an isotropic etch process that minimizes overetch into the substrate. An optional additional blocking dielectric layer, at least one charge storage element, a tunneling dielectric, and a semiconductor channel can be sequentially formed in the memory opening to provide a three-dimensional memory stack.
摘要翻译：第一隔离介电层通过交替的多个材料层和绝缘体层的堆叠形成在存储器开口中。具有底部开口的间隔物通过沉积保形材料层和各向异性蚀刻形成在第一阻挡介电层上。存储器开口底部的第一阻挡介质层的水平部分可以通过各向同性的蚀刻工艺进行蚀刻，该过程使过蚀刻最小化到衬底中。可以在存储器开口中顺序地形成可选的附加阻挡介质层，至少一个电荷存储元件，隧道电介质和半导体沟道，以提供三维存储堆叠。

9. 发明授权

US09379124B2 Vertical floating gate NAND with selectively deposited ALD metal films 有权
标题翻译：垂直浮栅NAND具有选择性沉积的ALD金属膜
公开(公告)号：US09379124B2
公开(公告)日：2016-06-28
申请号：US14314370
申请日：2014-06-25
申请人： SanDisk Technologies Inc.
发明人： Rahul Sharangpani , Raghuveer S. Makala , Thomas Jongwan Kwon , Senaka Kanakamedala , George Matamis
IPC分类号： G11C11/34 , H01L27/115 , H01L29/423 , G11C16/04 , G11C16/06 , H01L29/788 , H01L21/28 , H01L21/285 , H01L21/311 , H01L21/3205 , H01L21/02
CPC分类号： H01L27/11556 , G11C16/0408 , G11C16/06 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/28273 , H01L21/28556 , H01L21/28562 , H01L21/28568 , H01L21/31111 , H01L21/32055 , H01L27/11519 , H01L27/11524 , H01L29/42332 , H01L29/7883
摘要： A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.
摘要翻译：包括半导体通道和多个控制栅电极的单片三维NAND串的制造方法包括使用原子层沉积选择性地形成多个离散的电荷存储区域。多个离散电荷存储区域包括金属或导电金属氧化物中的至少一种。

10. 发明申请

US20160141294A1 THREE-DIMENSIONAL MEMORY STRUCTURE WITH MULTI-COMPONENT CONTACT VIA STRUCTURE AND METHOD OF MAKING THEREOF 有权
标题翻译：通过结构与多组分接触的三维存储结构及其制备方法
公开(公告)号：US20160141294A1
公开(公告)日：2016-05-19
申请号：US14926347
申请日：2015-10-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Somesh Peri , Sateesh Koka , Raghuveer S. Makala , Rahul Sharangpani , Matthias Baenninger , Jayavel Pachamuthu , Johann Alsmeier
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/1157 , H01L21/28512 , H01L21/28562 , H01L21/28568 , H01L21/76877 , H01L23/53266 , H01L27/11582 , H01L29/66553 , H01L29/78
摘要： A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor material.
摘要翻译：接触通孔结构可以包括通过在接触沟槽的底部的半导体表面上选择性沉积钌而形成的钌部分。含钌部分可以降低与下掺杂半导体区域的界面处的接触电阻。可以在接触沟槽的剩余容积中形成至少一个导电材料部分以形成接触通孔结构。或者或另外，接触通孔结构可以包括拉伸应力产生部分和导电材料部分。在接触通孔结构通过绝缘层的交替堆叠和包括压缩应力产生材料的导电层形成的情况下，拉伸应力产生部分可以至少部分地抵消由导电层产生的压缩应力。接触通孔结构的导电材料部分可以包括金属材料或掺杂的半导体材料。

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