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1. 发明授权

US11037648B2 Memory system for improving memory reliability and memory management method for the same 有权
公开(公告)号：US11037648B2
公开(公告)日：2021-06-15
申请号：US16051796
申请日：2018-08-01
申请人： SK hynix Inc.
发明人： Tae Sik Yun , Chun Seok Jeong
IPC分类号： G06F11/27 , G11C29/44 , G11C29/42 , G11C29/36 , G06F11/263
摘要： A memory system and a method for operating the same, wherein the memory system includes a first memory and a second memory each configured to store data. The memory system further includes a test and repair circuit operationally connected to the first memory and to the second memory. The test and repair circuit is configured to receive a test initiation signal and perform, in response to receiving the test initiation signal, a test operation on at least one of the first memory and the second memory. The test and repair circuit is also configured to perform, based on a result of the test operation, a repair operation on the at least one of the first memory and the second memory.

2. 发明授权

US11455703B2 Semiconductor device and semiconductor system including the same 有权
公开(公告)号：US11455703B2
公开(公告)日：2022-09-27
申请号：US16769877
申请日：2018-06-14
申请人： SK hynix Inc.
发明人： Chun Seok Jeong
IPC分类号： G06T1/20 , G06F13/38 , G06T1/60
摘要： In accordance with an embodiment of the present disclosure, a semiconductor system includes a first semiconductor device coupled to a first transmission line, and configured to transmit a first packet to a second transmission line on the basis of first destination information of the first packet received through the first transmission line; a second semiconductor device coupled to the first semiconductor device through the second transmission line, and configured to transmit a second packet to a third transmission line on the basis of second destination information of the second packet received through the second transmission line; and a third semiconductor device coupled to the second semiconductor device through the third transmission line, coupled to the first semiconductor device through the first transmission line, and configured to transmit a third packet to the first transmission line on the basis of third destination information of the third packet received through the third transmission line.

3. 发明授权

US09830956B2 Latch circuit and semiconductor apparatus including the same 有权
公开(公告)号：US09830956B2
公开(公告)日：2017-11-28
申请号：US15152800
申请日：2016-05-12
申请人： SK hynix Inc.
发明人： Chun Seok Jeong , Hyun Sung Lee
IPC分类号： G11C7/10 , H01L25/065
CPC分类号： G11C7/10 , G11C7/1012 , G11C7/1039 , H01L25/0657 , H01L2224/13025 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2225/06541 , H01L2924/15192 , H01L2924/15311
摘要： A latch circuit may be provided. The latch circuit may include a plurality of latches configured to store and output data through input/output signal lines according to input/output control signals. Latches coupled with input/output signal lines of same orders among the plurality of latches may be disposed by being distributed by orders of the input/output control signals. A plurality of pipe latches may be configured by latches which are inputted with input/output control signals of same orders, among the latches disposed by being distributed.

4. 发明授权

US09435851B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US09435851B2
公开(公告)日：2016-09-06
申请号：US14567853
申请日：2014-12-11
申请人： SK hynix Inc.
发明人： Chun Seok Jeong
IPC分类号： H03K3/00 , G01R31/28 , H03K3/03
CPC分类号： G01R31/2851 , G01R31/317 , H03K3/0315
摘要： A semiconductor apparatus includes a command decoding unit configured to decode an internal command, an internal clock and an internal clock enable signal, and generate an internal control signal; a clock enable signal control unit configured to receive a pre-clock enable signal and output one of the pre-clock enable signal and an enabled internal clock enable signal as the internal clock enable signal in response to a first test signal; an enable signal selection unit configured to output one of the pre-clock enable signal and a second to test signal as a counting enable signal in response to the first test signal; and a counting unit configured to perform a counting operation during an enable period of the counting enable signal, and output a counting code.
摘要翻译：半导体装置包括命令解码单元，被配置为对内部命令进行解码，内部时钟和内部时钟使能信号，并产生内部控制信号; 时钟使能信号控制单元，被配置为响应于第一测试信号而接收前置时钟使能信号并输出所述前置时钟使能信号中的一个和使能的内部时钟使能信号作为所述内部时钟使能信号; 使能信号选择单元，被配置为响应于所述第一测试信号，将所述前置时钟使能信号和第二测试信号之一输出作为计数使能信号; 以及计数单元，被配置为在所述计数使能信号的使能期间执行计数操作，并输出计数代码。

5. 发明授权

US10256799B2 Semiconductor apparatus and system including plurality of channels 有权
公开(公告)号：US10256799B2
公开(公告)日：2019-04-09
申请号：US14521113
申请日：2014-10-22
申请人： SK hynix Inc.
发明人： Chun Seok Jeong , Jung Hwan Lee
IPC分类号： H03K17/00 , H03K5/135
摘要： A semiconductor apparatus includes a direct access section, an interface section, and a through-via region. The direct access section receives first and second groups of input signals through a direct access pad, and generates first and second groups of control signals based on the first and second groups of input signals. The interface section comprises a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals. The through-via region electrically couples the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively.

6. 发明授权

US09275920B2 Semiconductor apparatus and stacked semiconductor apparatus for checking formation and connection of through silicon via 有权
标题翻译：用于检查硅通孔的形成和连接的半导体装置和堆叠半导体装置
公开(公告)号：US09275920B2
公开(公告)日：2016-03-01
申请号：US14216265
申请日：2014-03-17
申请人： SK hynix Inc.
发明人： Chun Seok Jeong , Jae Jin Lee
IPC分类号： H01L23/58 , H01L21/66 , H01L23/48 , G01R31/28 , H01L25/065 , H01L25/00
CPC分类号： H01L22/34 , G01R31/2884 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06596
摘要： A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.
摘要翻译：半导体装置包括被形成为与另一个芯片电连接的TSV以及被配置为检查TSV的电容分量以产生TSV异常信号的TSV测试单元。

7. 发明授权

US11483505B2 Image synchronization device and image information generation apparatus including the same 有权
公开(公告)号：US11483505B2
公开(公告)日：2022-10-25
申请号：US16769830
申请日：2018-06-14
申请人： SK hynix Inc.
发明人： Chang Hyun Kim , Wan Jun Roh , Doo Bock Lee , Seung Hun Lee , Jae Jin Lee , Chun Seok Jeong
IPC分类号： H04N5/376 , H04N5/369 , H04N5/05 , H04N5/341 , H04N5/372 , H04N17/00
摘要： In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

8. 发明授权

US11423959B2 Processing-in-memory devices for element-wise multiplication 有权
公开(公告)号：US11423959B2
公开(公告)日：2022-08-23
申请号：US17319660
申请日：2021-05-13
申请人： SK hynix Inc.
发明人： Mun Gyu Son , Chun Seok Jeong
IPC分类号： G11C7/10 , G06F7/544
摘要： A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

9. 发明授权

US09552894B2 Impedance calibration circuit, and semiconductor memory and memory system using the same 有权
标题翻译：阻抗校准电路，半导体存储器和存储器系统使用相同
公开(公告)号：US09552894B2
公开(公告)日：2017-01-24
申请号：US14564404
申请日：2014-12-09
申请人： SK hynix Inc.
发明人： Chun Seok Jeong
IPC分类号： H01L23/58 , G11C29/02 , G11C29/50 , G11C29/44
CPC分类号： G11C29/025 , G11C29/028 , G11C29/50008 , G11C2029/4402
摘要： An embodiment may include a first replica driver group configured for replicating an output driver of a physical area. A second replica driver group configured for replicating an output driver of a test electrode area for direct access of a memory, and an impedance calibration unit configured to independently perform an impedance matching operation of the first replica driver group and the second replica driver group.
摘要翻译：实施例可以包括被配置用于复制物理区域的输出驱动器的第一副本驱动器组。配置为复制用于存储器的直接访问的测试电极区域的输出驱动器的第二复制驱动器组，以及被配置为独立地执行第一副本驱动器组和第二副本驱动器组的阻抗匹配操作的阻抗校准单元。

10. 发明授权

US09379715B2 Semiconductor apparatus and system including plurality of channels 有权
标题翻译：包括多个通道的半导体装置和系统
公开(公告)号：US09379715B2
公开(公告)日：2016-06-28
申请号：US14521163
申请日：2014-10-22
申请人： SK hynix Inc.
发明人： Chun Seok Jeong
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03K5/135
摘要： A semiconductor apparatus includes a direct access section, an interface section, and a through-silicon via region. The direct access section receives a normal clock, a first clock, and a control signal through a direct access pad. The interface section comprises a plurality of channel circuits suitable for aligning the control signal to the first clock, and outputting an aligned control signal. The through-silicon via region transfers the normal clock and the aligned control signal from the interface section to a plurality of channels corresponding to the respective channel circuits.
摘要翻译：半导体装置包括直接存取部分，界面部分和穿硅通孔区域。直接访问部分通过直接访问板接收正常时钟，第一时钟和控制信号。接口部分包括适于将控制信号与第一时钟对准的多个通道电路，并输出对准的控制信号。贯通硅通孔区域将正常时钟和对准的控制信号从接口部分传送到对应于各个通道电路的多个通道。

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