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1. 发明授权

US09245976B2 Vertical channel transistor with self-aligned gate electrode and method for fabricating the same 有权
标题翻译：具有自对准栅电极的垂直沟道晶体管及其制造方法
公开(公告)号：US09245976B2
公开(公告)日：2016-01-26
申请号：US14512091
申请日：2014-10-10
申请人： SK hynix Inc.
发明人： Heung-Jae Cho , Eui-Seong Hwang , Eun-Shil Park
IPC分类号： H01L29/66 , H01L21/28 , H01L29/78 , H01L29/40 , H01L29/423 , H01L27/108
CPC分类号： H01L29/66666 , H01L21/28026 , H01L27/10814 , H01L27/10873 , H01L29/402 , H01L29/407 , H01L29/42356 , H01L29/42376 , H01L29/7827
摘要： A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.
摘要翻译：一种用于制造垂直沟道晶体管的方法，包括在衬底上形成横向相对的两个侧壁的多个柱; 在支柱的两个侧壁上形成栅介电层; 形成覆盖所述柱的任何一个侧壁的第一栅电极和覆盖所述柱的其它侧壁并且具有低于所述第一栅电极的高度的屏蔽栅电极; 以及形成与所述第一栅电极的侧壁的上部连接的第二栅电极。

2. 发明授权

US09236386B2 Semiconductor device with buried bit line and method for fabricating the same 有权
公开(公告)号：US09236386B2
公开(公告)日：2016-01-12
申请号：US14565222
申请日：2014-12-09
申请人： SK hynix Inc.
发明人： Heung-Jae Cho , Eui-Seong Hwang , Eun-Shil Park
IPC分类号： H01L27/108 , H01L27/06 , H01L21/8239 , H01L29/417 , H01L29/66 , H01L29/78 , H01L29/45
CPC分类号： H01L27/10885 , H01L21/8239 , H01L27/0629 , H01L27/10814 , H01L27/10876 , H01L29/41741 , H01L29/456 , H01L29/66666 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.

3. 发明授权

US09165924B2 Vertical channel type nonvolatile memory device and method for fabricating the same 有权
标题翻译：垂直通道型非易失性存储器件及其制造方法
公开(公告)号：US09165924B2
公开(公告)日：2015-10-20
申请号：US13788319
申请日：2013-03-07
申请人： SK hynix Inc.
发明人： Heung-Jae Cho , Yong-Soo Kim , Beom-Yong Kim , Won-Joon Choi , Jung-Ryul Ahn
IPC分类号： H01L29/792 , H01L27/088 , H01L27/115
CPC分类号： H01L27/088 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.
摘要翻译：一种用于制造垂直沟道型非易失性存储器件的方法包括：在半导体衬底上交替地形成多个牺牲层和多个层间电介质层; 蚀刻牺牲层和层间电介质层以形成多个用于通道的第一开口，每个开口暴露衬底; 填充第一开口以形成从半导体衬底突出的多个通道; 蚀刻牺牲层和层间电介质层以形成用于去除沟道之间的牺牲层的第二开口; 通过去除由第二开口暴露的牺牲层来暴露通道的侧壁; 以及在通道的暴露的侧壁上形成隧道绝缘层，电荷陷阱层，电荷阻挡层和用于栅电极的导电层。

4. 发明授权

US08847322B2 Dual polysilicon gate of a semiconductor device with a multi-plane channel 有权
标题翻译：具有多平面通道的半导体器件的双多晶硅栅极
公开(公告)号：US08847322B2
公开(公告)日：2014-09-30
申请号：US13926974
申请日：2013-06-25
申请人： SK hynix Inc.
发明人： Kwan-Yong Lim , Heung-Jae Cho , Min-Gyu Sung
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/28 , H01L27/105 , H01L29/78 , H01L21/225
CPC分类号： H01L29/7831 , H01L21/2256 , H01L21/28035 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L27/105 , H01L27/1052 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.
摘要翻译：半导体器件的双多晶硅栅极包括具有第一区域，第二区域和第三区域的衬底，以及形成在第一区域的衬底中的突出结构的沟道区域，形成在衬底上的栅极绝缘层形成在所述第一和第二区域的栅极绝缘层上的第一多晶硅层，形成在所述第三区域的所述栅极绝缘层上的第二多晶硅层和掺杂有杂质的绝缘层，在通道区域的第一多晶硅层的内部。

5. 发明授权

US08796090B2 Semiconductor device with vertical channel transistor and method for fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08796090B2
公开(公告)日：2014-08-05
申请号：US13716931
申请日：2012-12-17
申请人： SK hynix Inc.
发明人： Heung-Jae Cho , Tae-Yoon Kim
IPC分类号： H01L21/8242
CPC分类号： H01L29/66666 , H01L21/8239 , H01L27/1052 , H01L27/10876 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device includes forming a plurality of semiconductor body lines in which a plurality of buried bit lines are buried, to be separated by a plurality of trenches, forming a filling layer that fills each of the plurality of trenches, forming a conductive layer over the plurality of semiconductor body lines and the filling layer, forming a plurality of semiconductor pillars over the plurality of semiconductor body lines by etching the conductive layer.
摘要翻译：一种制造半导体器件的方法，包括：形成多个埋置位线的多个半导体本体线，被多个沟槽隔开，形成填充多个沟槽中的每一个的填充层，形成在所述多个半导体体线和所述填充层上形成导电层，通过蚀刻所述导电层在所述多个半导体主体线上形成多个半导体柱。

6. 发明授权

US09064854B2 Semiconductor device with gate stack structure 有权
标题翻译：具有栅极堆叠结构的半导体器件
公开(公告)号：US09064854B2
公开(公告)日：2015-06-23
申请号：US13891648
申请日：2013-05-10
申请人： SK hynix Inc.
发明人： Kwan-Yong Lim , Hong-Seon Yang , Heung-Jae Cho , Tae-Kyung Kim , Yong-Soo Kim , Min-Gyu Sung
IPC分类号： H01L29/423 , H01L29/788 , H01L29/49 , H01L29/51 , H01L21/28
CPC分类号： H01L29/4925 , H01L21/28061 , H01L29/42324 , H01L29/4941 , H01L29/513 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.
摘要翻译：半导体器件包括第一导电层，第一导电层上的第一中间结构，第一中间结构之上的第二中间结构以及第二中间结构上的第二导电层。第一中间结构包括金属硅化物层和含氮金属层。第二中间结构至少包括含氮金属硅化物层。

7. 发明授权

US08895392B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08895392B2
公开(公告)日：2014-11-25
申请号：US13720059
申请日：2012-12-19
申请人： SK hynix Inc.
发明人： Tae-Yoon Kim , Heung-Jae Cho
IPC分类号： H01L21/336 , H01L21/02
CPC分类号： H01L21/02697 , H01L21/743 , H01L27/10885
摘要： A method for fabricating a semiconductor device including a semiconductor substrate having a trench formed therein. A migration assist layer is formed in the trench and on the substrate. A buried layer in formed in the trench by migrating material from the migration assist layer and the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，该半导体器件包括其中形成有沟槽的半导体衬底。在沟槽和衬底上形成迁移辅助层。通过从迁移辅助层和半导体衬底迁移材料而形成在沟槽中的掩埋层。

8. 发明授权

US09236327B2 Semiconductor device with buried bit line and method for fabricating the same 有权
标题翻译：具有掩埋位线的半导体器件及其制造方法
公开(公告)号：US09236327B2
公开(公告)日：2016-01-12
申请号：US14264832
申请日：2014-04-29
申请人： SK hynix Inc.
发明人： Heung-Jae Cho , Bong-Seok Jeon
IPC分类号： H01L27/108 , H01L23/48 , H01L29/66 , H01L21/74
CPC分类号： H01L23/481 , H01L21/743 , H01L27/108 , H01L27/10885 , H01L29/66666 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines.
摘要翻译：半导体器件包括：形成在衬底中的冲压停止区域; 形成在所述基板上的多个掩埋位线; 形成在所述掩埋位线之上的多个柱结构; 多个字线延伸以与埋置的位线相交并与柱结构接触; 以及将字线与掩埋位线隔离的隔离层。

9. 发明授权

US08906775B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08906775B2
公开(公告)日：2014-12-09
申请号：US13717512
申请日：2012-12-17
申请人： SK Hynix Inc.
发明人： Heung-Jae Cho , Eui-Seong Hwang , Tae-Yoon Kim , Kyu-Hyung Yoon
IPC分类号： H01L21/30 , H01L29/02 , H01L49/02 , H01L21/18 , H01L27/108
CPC分类号： H01L29/02 , H01L21/185 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10891 , H01L28/40
摘要： A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.
摘要翻译：一种制造半导体器件的方法包括在第一半导体衬底上形成第一半导体晶片，其中电路部分和第一接合层堆叠在其中，形成第二半导体晶片，其包括结构和用于间隙填充的绝缘层在所述结构之间，在第二半导体衬底上，包括堆叠在其中的柱和位线的结构，将所述第一半导体晶片与所述第二半导体晶片接合，使得所述第一结合层面向所述绝缘层，以及将所述第二半导体衬底与所述第二半导体衬底分离粘合的第二半导体晶片。

10. 发明授权

US08772862B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08772862B2
公开(公告)日：2014-07-08
申请号：US13711673
申请日：2012-12-12
申请人： SK hynix Inc.
发明人： Heung-Jae Cho
IPC分类号： H01L29/66
CPC分类号： H01L29/1608 , H01L21/26506 , H01L27/10808 , H01L27/10873 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66666 , H01L29/7827
摘要： A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area.
摘要翻译：垂直沟道晶体管包括形成在衬底上的柱和形成在柱的侧壁上的栅电极，其中柱包括源区，源区上的垂直沟道区，垂直沟道区上的漏区，以及设置在垂直沟道区域和漏极区域之间的防漏区域。

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