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1. 发明申请

US20230056231A1 MEMORY, MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM 有权
公开(公告)号：US20230056231A1
公开(公告)日：2023-02-23
申请号：US17532826
申请日：2021-11-22
申请人： SK hynix Inc.
发明人： Munseon JANG , Hoiju CHUNG , Jang Ryul KIM
IPC分类号： G11C29/42 , G11C29/12 , G11C29/00 , G11C7/10
摘要： A memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.

2. 发明公开

US20240029810A1 MEMORY, MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM 审中-公开
公开(公告)号：US20240029810A1
公开(公告)日：2024-01-25
申请号：US18482016
申请日：2023-10-06
申请人： SK hynix Inc.
发明人： Munseon JANG , Hoiju CHUNG , Jang Ryul KIM
IPC分类号： G11C29/42 , G11C7/10 , G11C29/00 , G11C29/12
CPC分类号： G11C29/42 , G11C7/1039 , G11C29/702 , G11C29/1201
摘要： A memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.

3. 发明申请

US20170123896A1 MEMORY DEVICE AND SYSTEM INCLUDING ON CHIP ECC CIRCUIT 审中-公开
公开(公告)号：US20170123896A1
公开(公告)日：2017-05-04
申请号：US15061412
申请日：2016-03-04
申请人： SK hynix Inc.
发明人： Jin Ho BAEK , Jang Ryul KIM , Il PARK , Ho Kyoon LEE
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F11/10 , G06F11/1048 , G06F11/1076
摘要： An on-chip logic block may include a host ECC circuit configured to correct an error based on host parity. The on-chip logic block may include a memory ECC circuit configured to correct an error based on memory parity.

4. 发明申请

US20210397516A1 MEMORY AND OPERATION METHOD OF MEMORY 有权
公开(公告)号：US20210397516A1
公开(公告)日：2021-12-23
申请号：US17330881
申请日：2021-05-26
申请人： SK hynix Inc.
发明人： Munseon JANG , Hoiju CHUNG , Jang Ryul KIM
IPC分类号： G06F11/10 , H03M13/00
摘要： A memory includes: a memory core including sequentially disposed N data cell regions and an ECC cell region respectively suitable for storing N data pieces of K bits and a corresponding ECC of M bits; and an error correction circuitry suitable for generating the ECC based on the data pieces and error-correcting the data pieces based on the ECC, through a check matrix configured by a message part of a [M×(K*N)] bit-dimension and an ECC part of a [M×M] bit-dimension, wherein the message part includes N characteristic indicator groups of a [M/2×K] bit-dimension, respectively corresponding to the data pieces, and each including K indicators of a [M/2×1] bit-dimension and having the same value, and wherein a hamming distance between the indicators respectively corresponding to the data pieces stored in neighboring ones among the data cell regions is 1 or M/2.

5. 发明申请

US20140328104A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140328104A1
公开(公告)日：2014-11-06
申请号：US14071230
申请日：2013-11-04
申请人： SK hynix Inc.
发明人： Seon Kwang JEON , Sung Soo RYU , Chang Il KIM , Jang Ryul KIM
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/04 , H01L25/0657 , H01L2224/16145
摘要： A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.
摘要翻译：堆叠在逻辑芯片上的逻辑芯片和存储器芯片，逻辑芯片具有面向存储器芯片的第一表面和与第一表面相对的第二表面，并且包括：用于交换信号的第一和第二内部输入/输出电路单元; 第一外部输入/输出电路单元，用于通过在第二表面上的第一存储器的外部接口标准形成的第一外部输入/输出焊盘交换信号; 以及第二外部输入/输出电路单元，用于通过在第二表面上根据第二存储器的外部接口标准形成的第二外部输入/输出焊盘来交换信号，其中半导体器件以第一模式中的一个工作，其中第一内部输入 /输出电路单元和第一外部输入/输出电路单元被使能，其中第一和第二内部输入/输出电路单元和第二外部输入/输出电路单元被使能的第二模式。

6. 发明公开

US20230222033A1 MEMORY AND OPERATION METHOD OF MEMORY 审中-公开
公开(公告)号：US20230222033A1
公开(公告)日：2023-07-13
申请号：US18174648
申请日：2023-02-27
申请人： SK hynix Inc.
发明人： Munseon JANG , Hoi Ju CHUNG , Jang Ryul KIM
IPC分类号： G06F11/10 , G06F3/06
CPC分类号： G06F11/1076 , G06F3/0673 , G06F3/0659 , G06F3/0619
摘要： A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.

7. 发明申请

US20210397515A1 MEMORY AND OPERATION METHOD OF MEMORY 有权
公开(公告)号：US20210397515A1
公开(公告)日：2021-12-23
申请号：US17329681
申请日：2021-05-25
申请人： SK hynix Inc.
发明人： Munseon JANG , Hoi Ju CHUNG , Jang Ryul KIM
IPC分类号： G06F11/10 , G06F3/06
摘要： A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.

8. 发明申请

US20210397355A1 MEMORY, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY SYSTEM 有权
公开(公告)号：US20210397355A1
公开(公告)日：2021-12-23
申请号：US17354482
申请日：2021-06-22
申请人： SK hynix Inc.
发明人： Munseon JANG , Hoiju CHUNG , Jang Ryul KIM
IPC分类号： G06F3/06
摘要： A memory includes: a non-volatile memory suitable for storing a defect address; a register suitable for receiving and storing the defect address from the non-volatile memory during a boot-up operation, and receiving and storing an address that is input from an exterior during a register access operation; a comparison circuit suitable for comparing the address stored in the register with an address that is input from the exterior to produce a comparison result; redundant memory cells that are accessed according to the comparison result of the comparison circuit and a redundancy activation bit; and normal memory cells that are accessed according to the comparison result of the comparison circuit and the redundancy activation bit.

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