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1. 发明授权

US11387216B2 Semiconductor memory device 有权
公开(公告)号：US11387216B2
公开(公告)日：2022-07-12
申请号：US16907094
申请日：2020-06-19
申请人： SK hynix Inc.
发明人： Jin Ho Kim , Young Ki Kim , Sang Hyun Sung , Sung Lae Oh , Byung Hyun Jun
IPC分类号： H01L25/065 , H01L25/18 , H01L23/00 , H01L23/552 , H01L49/02
摘要： A semiconductor memory device includes a plurality of first pads disposed in one surface of a memory chip which includes a memory cell array and a plurality of row lines coupled to the memory cell array, and coupled to the row lines, respectively; and a plurality of second pads disposed in one surface of a circuit chip which is boned to the one surface of the memory chip, coupled to pass transistors, respectively, of the circuit chip, and bonded to the first pads, respectively. The second pads are aligned with the pass transistors, with the same pitch as a pitch of the pass transistors.

2. 发明授权

US11380702B2 Memory device having vertical structure 有权
公开(公告)号：US11380702B2
公开(公告)日：2022-07-05
申请号：US17145209
申请日：2021-01-08
申请人： SK hynix Inc.
发明人： Jin Ho Kim , Kwang Hwi Park , Sang Hyun Sung , Sung Lae Oh , Chang Woon Choi
IPC分类号： H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L27/11526
摘要： A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

3. 发明授权

US11569265B2 Three-dimensional memory device and manufacturing method thereof 有权
公开(公告)号：US11569265B2
公开(公告)日：2023-01-31
申请号：US17145229
申请日：2021-01-08
申请人： SK hynix Inc.
发明人： Sung Lae Oh , Jin Ho Kim , Sang Woo Park , Sang Hyun Sung
IPC分类号： H01L27/11582 , H01L23/522 , H01L21/768 , H01L27/11556 , H01L23/528
摘要： A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers.

4. 发明授权

US11527544B2 Three-dimensional memory device and manufacturing method thereof 有权
公开(公告)号：US11527544B2
公开(公告)日：2022-12-13
申请号：US17014370
申请日：2020-09-08
申请人： SK hynix Inc.
发明人： Sang Hyun Sung , Jin Ho Kim , Sung Lae Oh
IPC分类号： H01L27/11539 , H01L23/528 , H01L27/11556 , H01L27/11582
摘要： A three-dimensional memory device includes an electrode structure including a plurality of interlayer dielectric layers and a plurality of electrode layers which are alternately stacked on a first substrate, each of the plurality of electrode layers having a pad part which does not overlap with another electrode layer positioned on the electrode layer; a pass transistor positioned below the first substrate; and a first contact passing through the electrode structure from the pad part of one of the plurality of electrode layers, and coupling the pad part and the pass transistor.

5. 发明授权

US09553106B1 Three-dimensional nonvolatile memory device 有权
标题翻译：三维非易失性存储器件
公开(公告)号：US09553106B1
公开(公告)日：2017-01-24
申请号：US15047748
申请日：2016-02-19
申请人： SK hynix Inc.
发明人： Sang Hyun Sung , Jeong Hwan Kim , Jin Ho Kim
IPC分类号： H01L27/115 , H01L23/528 , H01L23/522
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/528 , H01L27/11575
摘要： A three-dimensional nonvolatile memory device includes a substrate defined with a slimming region, first and second pass regions on both sides of the slimming region, and a cell region adjacent to the slimming region with the first pass region interposed therebetween; a word line stack including a plurality of word lines stacked over the cell region, the first pass region, and the slimming region of the substrate; first wiring lines extending from the slimming region to the first pass region and electrically coupling some word lines with pass transistors formed in the first pass region of the substrate; and second wiring lines extending from the slimming region to the second pass region and electrically coupling remaining word lines, other than the some word lines, with pass transistors formed in the second pass region of the substrate.
摘要翻译：三维非易失性存储器件包括限定有减肥区域的基底，在减肥区域的两侧上的第一和第二通过区域以及与所述减肥区域相邻的细胞区域，其间插入有第一通过区域; 包括堆叠在所述基板的所述单元区域，所述第一通过区域和所述减薄区域上的多个字线的字线堆叠; 从所述减肥区域延伸到所述第一通过区域的第一布线，并且将形成在所述基板的所述第一通过区域中的通过晶体管电耦合一些字线; 以及从所述减肥区域延伸到所述第二通过区域的第二布线，并且将除了所述一些字线之外的剩余字线与形成在所述基板的第二通过区域中的通过晶体管电连接。

6. 发明授权

US09515084B2 3D nonvolatile memory device having common word line 有权
标题翻译：具有公共字线的3D非易失性存储器件
公开(公告)号：US09515084B2
公开(公告)日：2016-12-06
申请号：US14667397
申请日：2015-03-24
申请人： SK hynix Inc.
发明人： Sung Lae Oh , Jin Ho Kim
IPC分类号： H01L23/52 , H01L27/11 , H01L21/76 , H01L21/32 , H01L27/115 , H01L21/768 , H01L21/3213
CPC分类号： H01L27/11578 , H01L21/32139 , H01L21/768 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L27/11582
摘要： A 3D nonvolatile memory device including memory cells vertically stacked is disclosed. Word lines are integrally formed to be elongated over adjacent cell regions spaced apart from each other, and portions of the word lines between the cell regions are partially etched in a stepped shape to form word line contact regions.
摘要翻译：公开了一种包括垂直堆叠的存储单元的3D非易失性存储器件。字线一体地形成为在彼此间隔开的相邻单元区域上延伸，并且单元区域之间的字线的部分被部分地蚀刻成台阶形状以形成字线接触区域。

7. 发明授权

US11315914B2 Three-dimensional semiconductor memory device 有权
公开(公告)号：US11315914B2
公开(公告)日：2022-04-26
申请号：US16890653
申请日：2020-06-02
申请人： SK hynix Inc.
发明人： Sang Hyun Sung , Young Ki Kim , Jin Ho Kim , Byung Hyun Jun
IPC分类号： H01L27/11582 , H01L25/18 , H01L23/00 , H01L27/11573 , H01L23/528
摘要： A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.

8. 发明授权

US09595331B1 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US09595331B1
公开(公告)日：2017-03-14
申请号：US15019450
申请日：2016-02-09
申请人： SK hynix Inc.
发明人： Go-Hyun Lee , Jin Ho Kim , Ji Hui Baek , Sung Wook Jung
IPC分类号： G11C16/08 , G11C16/04 , G11C16/28 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/08
摘要： A nonvolatile memory device may include a plurality of memory blocks each including a drain select line, word lines and a source select line, and a pass transistor stage including a plurality of pass transistors formed in series in an active region and suitable for transferring word line voltages to a memory block selected among the memory blocks, in response to a block select signal, wherein the pass transistors each share a drain with a first adjacent pass transistor at one side while sharing a source with a second adjacent pass transistor at the other, and wherein a pair of pass transistors which share the source transfer word line driving signal form drains thereof to a pair of word lines which are included in different memory blocks among the memory blocks, through the source.
摘要翻译：非易失性存储器件可以包括多个存储块，每个存储块包括漏极选择线，字线和源极选择线，以及包括在有源区域中串联形成并适于传输字线的多个通过晶体管级的通过晶体管级响应于块选择信号，在存储块中选择的存储块的电压，其中传输晶体管在一侧与第一相邻传输晶体管共享漏极，而在另一侧与第二相邻传输晶体管共享源极，并且其中共享所述源极传输字线驱动信号的一对传输晶体管通过所述源将所述源极传输字线驱动信号的漏极形成为包含在所述存储器块之间的不同存储器块中的一对字线。

9. 发明授权

US11637095B2 Three-dimensional semiconductor memory device 有权
公开(公告)号：US11637095B2
公开(公告)日：2023-04-25
申请号：US17155600
申请日：2021-01-22
申请人： SK hynix Inc.
发明人： Seong Ho Choi , Jin Ho Kim
IPC分类号： H01L25/18 , G11C16/08 , H01L23/00 , H01L25/065 , H01L27/11556 , H01L27/11582
摘要： A three-dimensional semiconductor memory device may include a cell wafer including a source plate, a plurality of first word lines stacked to be spaced apart from one another along a plurality of first vertical channels projecting from a bottom surface of the source plate in a vertical direction, and a plurality of second word lines stacked to be spaced apart from one another along a plurality of second vertical channels projecting from a top surface of the source plate in a vertical direction; a first peripheral wafer bonded to a bottom surface of the cell wafer, and including a first row decoder unit which transfers an operating voltage to the plurality of first word lines; and a second peripheral wafer bonded to a top surface of the cell wafer, and including a second row decoder unit which transfers an operating voltage to the plurality of second word lines.

10. 发明授权

US11342353B2 Semiconductor memory device having three-dimensional structure and method for manufacturing the same 有权
公开(公告)号：US11342353B2
公开(公告)日：2022-05-24
申请号：US16779599
申请日：2020-02-01
申请人： SK hynix Inc.
发明人： Sung Lae Oh , Jin Ho Kim , Sang Woo Park , Sang Hyun Sung , Soo Nam Jung , Chang Woon Choi
IPC分类号： H01L27/11582 , H01L21/768 , H01L23/00 , H01L27/11556 , H01L21/311 , H01L23/528 , H01L27/11526 , H01L25/18 , H01L21/033 , H01L21/02 , H01L29/66 , H01L27/11573
摘要： A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.

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