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1. 发明申请

US20230100075A1 MEMORY DEVICE HAVING VERTICAL STRUCTURE 有权
公开(公告)号：US20230100075A1
公开(公告)日：2023-03-30
申请号：US18058795
申请日：2022-11-25
申请人： SK hynix Inc.
发明人： Sung Lae OH , Sang Woo PARK , Dong Hyuk CHAE , Ki Soo KIM
IPC分类号： H01L27/11556 , H01L27/11582 , H01L27/11573 , H01L29/417 , H01L23/00 , G11C16/24 , G11C16/08 , H01L25/18 , H01L27/02 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11565 , H01L27/1157 , H01L29/06
摘要： A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

2. 发明申请

US20220122932A1 MEMORY DEVICE HAVING VERTICAL STRUCTURE 有权
公开(公告)号：US20220122932A1
公开(公告)日：2022-04-21
申请号：US17210698
申请日：2021-03-24
申请人： SK hynix Inc.
发明人： Sung Lae OH , Sang Woo PARK , Dong Hyuk CHAE , Ki Soo KIM
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , G11C16/08
摘要： A memory device having a vertical structure includes a memory cell array defined in a cell wafer, and having a plurality of word lines extending in a first direction and arranged in a second direction, and having a plurality of bit lines extending in the second direction and arranged in the first direction; and a logic circuit configured to control the memory cell array, and including a page buffer low-voltage circuit, a page buffer high-voltage circuit, a row decoder circuit and a peripheral circuit, wherein the page buffer low-voltage circuit is disposed in a first peripheral wafer and the page buffer high-voltage circuit, the row decoder circuit and the peripheral circuit are disposed in a second peripheral wafer, and wherein the cell wafer overlaps with the first peripheral wafer and the second peripheral wafer in a vertical direction that is perpendicular to a plane formed by the first direction and the second direction.

3. 发明申请

US20170033690A1 VOLTAGE GENERATION CIRCUIT 有权
标题翻译：电压发生电路
公开(公告)号：US20170033690A1
公开(公告)日：2017-02-02
申请号：US14957976
申请日：2015-12-03
申请人： SK hynix Inc.
发明人： Ki Soo KIM
IPC分类号： H02M3/158
CPC分类号： H02M3/07
摘要： A voltage generation circuit includes a voltage detection unit configured to detect a voltage level of an internal voltage and generate a detection signal, a first voltage control unit configured to be applied with a driving voltage and generate a voltage control signal in response to the detection signal, a voltage generation unit configured to generate the internal voltage in response to the voltage control signal, and a second voltage control unit configured to change a voltage level of the driving voltage in response to a voltage generation enable signal and the detection signal.
摘要翻译：电压产生电路包括：电压检测单元，被配置为检测内部电压的电压电平并产生检测信号;第一电压控制单元，被配置为施加驱动电压，并响应于检测信号产生电压控制信号电压产生单元，被配置为响应于电压控制信号而产生内部电压;以及第二电压控制单元，被配置为响应于电压产生使能信号和检测信号而改变驱动电压的电压电平。

4. 发明申请

US20210384160A1 MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND WRITE METHOD THEREOF 有权
公开(公告)号：US20210384160A1
公开(公告)日：2021-12-09
申请号：US17078020
申请日：2020-10-22
申请人： SK hynix Inc.
发明人： Sung Lae OH , Ki Soo KIM , Sang Woo PARK , Dong Hyuk CHAE
IPC分类号： H01L25/065 , H01L27/11582 , H01L27/11573 , H01L23/00 , G11C16/04 , G11C16/10 , G11C16/16
摘要： A memory device includes a first memory block defined in a first wafer; and a second memory block defined in a second wafer that is disposed in a vertical direction with respect to the first wafer. A size of the first memory block is smaller than a size of the second memory block.

5. 发明申请

US20210375901A1 MEMORY DEVICE HAVING VERTICAL STRUCTURE 有权
公开(公告)号：US20210375901A1
公开(公告)日：2021-12-02
申请号：US17062834
申请日：2020-10-05
申请人： SK hynix Inc.
发明人： Sung Lae OH , Sang Woo PARK , Dong Hyuk CHAE , Ki Soo KIM
IPC分类号： H01L27/11556 , G11C16/24 , G11C16/08 , H01L25/18 , H01L27/02 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/06 , H01L29/417 , H01L23/00
摘要： A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

6. 发明申请

US20210383874A1 MEMORY DEVICE HAVING VERTICAL STRUCTURE 有权
公开(公告)号：US20210383874A1
公开(公告)日：2021-12-09
申请号：US17087096
申请日：2020-11-02
申请人： SK hynix Inc.
发明人： Sung Lae OH , Sang Woo PARK , Dong Hyuk CHAE , Ki Soo KIM
IPC分类号： G11C16/24 , G11C16/08 , H01L27/11539 , H01L27/11556 , H01L27/11573 , H01L27/11582
摘要： A memory device includes a cell wafer including a memory cell array; a first logic wafer bonded to one surface of the cell wafer, and including a first logic circuit which controls the memory cell array; and a second logic wafer bonded to the other surface of the cell wafer which faces away from the one surface, and including a second logic circuit which controls the memory cell array.

7. 发明申请

US20170200480A1 VOLTAGE REGULATOR, MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF 有权
公开(公告)号：US20170200480A1
公开(公告)日：2017-07-13
申请号：US15473139
申请日：2017-03-29
申请人： SK hynix Inc.
发明人： Ki Soo KIM , Jin Seong KANG
IPC分类号： G11C5/14 , H02M3/07
CPC分类号： G11C5/147 , G11C5/145 , H02M3/07
摘要： Provided herein are a voltage regulator, a memory system having the same and an operation method thereof. The memory system includes a memory device configured to store data, a controller configured to control the memory device, and a voltage regulator configured to supply a pump-out voltage to the memory device or the controller so that the memory device or the controller is operated in the following manner: until a level of the pump-out voltage is increased to a second reference voltage lower than a first reference voltage, the pump-out voltage is output using a clock having a first frequency; when the pump-out voltage exceeds the second reference voltage and does not exceed the first reference voltage, the pump-out voltage is output using a clock having a second frequency lower than the first frequency; and when the pump-out voltage exceeds the first reference voltage, the pump-out voltage is output using the clock having the first frequency.

8. 发明申请

US20220115357A1 MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND WRITE METHOD THEREOF 有权
公开(公告)号：US20220115357A1
公开(公告)日：2022-04-14
申请号：US17555383
申请日：2021-12-18
申请人： SK hynix Inc.
发明人： Sung Lae OH , Ki Soo KIM , Sang Woo PARK , Dong Hyuk CHAE
IPC分类号： H01L25/065 , H01L27/11582 , H01L27/11573 , H01L23/00 , G11C16/10 , G11C16/16 , G11C16/04
摘要： A memory device includes: a first wafer including a first substrate, a plurality of first electrode layers and a plurality of first interlayer dielectric layers alternately stacked along first vertical channels projecting in a vertical direction on a top surface of the first substrate, and a dielectric stack comprising a plurality of dielectric layers and the plurality of first interlayer dielectric layers alternately stacked on the top surface of the first substrate; and a second wafer disposed on the first wafer, and including a second substrate, and a plurality of second electrode layers that are alternately stacked with a plurality of second interlayer dielectric layers along second vertical channels projecting in the vertical direction on a bottom surface of the second substrate and have pad parts overlapping with the dielectric stack in the vertical direction.

9. 发明申请

US20170085171A1 VOLTAGE REGULATOR, MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF 有权
公开(公告)号：US20170085171A1
公开(公告)日：2017-03-23
申请号：US15049759
申请日：2016-02-22
申请人： SK hynix Inc.
发明人： Ki Soo KIM , Jin Seong KANG
IPC分类号： H02M3/07 , G11C5/14
CPC分类号： G11C5/147 , G11C5/145 , H02M3/07
摘要： Provided herein are a voltage regulator, a memory system having the same and an operation method thereof. The memory system includes a memory device configured to store data, a controller configured to control the memory device, and a voltage regulator configured to supply a pump-out voltage to the memory device or the controller so that the memory device or the controller is operated in the following manner: until a level of the pump-out voltage is increased to a second reference voltage lower than a first reference voltage, the pump-out voltage is output using a clock having a first frequency; when the pump-out voltage exceeds the second reference voltage and does not exceed the first reference voltage, the pump-out voltage is output using a clock having a second frequency lower than the first frequency; and when the pump-out voltage exceeds the first reference voltage, the pump-out voltage is output using the clock having the first frequency.

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