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1. 发明授权

US09922728B2 Memory device 有权
公开(公告)号：US09922728B2
公开(公告)日：2018-03-20
申请号：US15066633
申请日：2016-03-10
申请人： SK hynix Inc.
发明人： Min-Su Park , Jae-Il Kim
IPC分类号： G11C29/56 , G11C29/52 , G11C11/406 , G11C29/50
CPC分类号： G11C29/52 , G11C11/406 , G11C29/50016 , G11C2211/4062
摘要： A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.

2. 发明授权

US10043569B2 Memory device for detecting failure of memory cells and refreshing memory cells 有权
公开(公告)号：US10043569B2
公开(公告)日：2018-08-07
申请号：US15066841
申请日：2016-03-10
申请人： SK hynix Inc.
发明人： Min-Su Park , Jae-Il Kim
IPC分类号： G06F11/07 , G11C11/406 , G11C11/4091 , G11C29/00
摘要： A memory device may include a plurality of memory cells; a refresh counter suitable for generating a refresh address; an address storage circuit suitable for storing an additional refresh address; an error detection unit suitable for detecting an error of selected memory cells of the plurality of memory cells in response to a refresh command in a detection period; and a refresh control unit suitable for refreshing memory cells corresponding to the refresh address or the additional refresh address among the memory cells in response to the refresh command, and controlling the refreshing of the memory cells to be delayed in the detection period.

3. 发明授权

US10014071B2 Comparing twice-read memory cell data for error detection in a memory device 有权
公开(公告)号：US10014071B2
公开(公告)日：2018-07-03
申请号：US15066773
申请日：2016-03-10
申请人： SK hynix Inc.
发明人： Min-Su Park , Jae-Il Kim , Tae-Kyun Kim , Jun-Gi Choi
IPC分类号： G11C29/08 , G11C11/406 , G11C11/4091 , G11C29/00
CPC分类号： G11C29/08 , G11C11/406 , G11C11/40611 , G11C11/4091 , G11C29/00 , G11C29/1201 , G11C29/18 , G11C29/50012 , G11C29/50016 , G11C2029/1202 , G11C2029/1204 , G11C2029/5002
摘要： A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.

4. 发明授权

US09336857B2 Semiconductor memory device including stacked memory chips 有权
标题翻译：半导体存储器件包括堆叠的存储器芯片
公开(公告)号：US09336857B2
公开(公告)日：2016-05-10
申请号：US14535075
申请日：2014-11-06
申请人： SK hynix Inc.
发明人： Min-Su Park , Young-Jun Ku
IPC分类号： G11C11/4093 , G11C7/10
CPC分类号： G11C11/4093 , G11C7/10 , G11C7/1066
摘要： A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.
摘要翻译：半导体存储器件包括：适于产生多个第一控制信号的主芯片和基于读命令的第二控制信号; 以及多个从属芯片，每个从属芯片适合于锁存从包括在相应的从芯片中的多个存储器单元读取的数据，并且基于第一控制信号的对应控制信号将锁存的数据发送到主芯片，其中主芯片锁存基于第一控制信号从副芯片发送的数据，并且基于第二控制信号输出锁存在主芯片中的数据。

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