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1. 发明授权

US09305895B2 Substrates having ball lands, semiconductor packages including the same, and methods of fabricating semiconductor packages including the same 有权
标题翻译：具有球形接地面的基板，包括其的半导体封装以及制造包括该基板的半导体封装的方法
公开(公告)号：US09305895B2
公开(公告)日：2016-04-05
申请号：US14262537
申请日：2014-04-25
申请人： SK hynix Inc.
发明人： Jong Woo Yoo , Qwan Ho Chung
IPC分类号： H01L23/00 , H05K1/11 , H01L23/31 , H01L23/498 , H05K3/40
CPC分类号： H01L24/81 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/85 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/16237 , H01L2224/32225 , H01L2224/48225 , H01L2224/81191 , H01L2224/81447 , H01L2224/85181 , H01L2224/85447 , H01L2924/00014 , H01L2924/12042 , H01L2924/1304 , H01L2924/14 , H01L2924/181 , H05K1/113 , H05K3/4007 , H05K2201/09663 , H05K2203/1178 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A package substrate includes a core layer having a first surface and a second surface which are opposite to each other, a ball land pad disposed on the first surface of the core layer, an opening that penetrates the core layer to expose the ball land pad, and a dummy ball land disposed on the second surface of the core layer to surround the opening. The dummy ball land includes at least one sub-pattern and at least one vent hole. Related semiconductor packages and related methods are also provided.
摘要翻译：封装基板包括具有彼此相对的第一表面和第二表面的芯层，设置在芯层的第一表面上的焊盘焊盘，穿过芯层以露出焊盘焊盘的开口，以及设置在芯层的第二表面上以围绕开口的虚拟球形区域。虚拟球场包括至少一个子图案和至少一个通气孔。还提供了相关的半导体封装和相关方法。

2. 发明授权

US09412716B2 Semiconductor package and method for manufacturing the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US09412716B2
公开(公告)日：2016-08-09
申请号：US14284637
申请日：2014-05-22
申请人： SK hynix Inc.
发明人： Jin Ho Bae , Qwan Ho Chung , Seong Kweon Ha , Jong Hyun Kim , Bok Gyu Min , Jae Won Shin
IPC分类号： H01L23/34 , H01L23/00 , H01L21/48 , H01L23/12 , H01L23/498 , H01L21/66
CPC分类号： H01L24/85 , H01L21/481 , H01L22/32 , H01L23/12 , H01L23/49838 , H01L23/49894 , H01L2224/05553 , H01L2224/05554 , H01L2224/48091 , H01L2224/73265 , H01L2224/85 , H01L2924/00014 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A method of manufacturing a semiconductor package includes: forming a strip substrate including a plurality of unit substrates, each being provided with a first connection pad and a second connection pad on a first surface of the unit substrate and each unit substrate being electrically and physically isolated from each other with the intervention of saw lines, first ground connection pads formed on the respective unit substrates, each of the first ground connection pads being electrically coupled with the first connection pad over the respective unit substrates, second ground connection pads formed on the saw line on the first surface side of the unit substrates and electrically isolated from the unit substrates, and test wiring formed on the saw line, the test wiring being electrically isolated from the unit substrates and electrically coupled with the second ground connection pads; and attaching semiconductor chips onto the respective unit substrates.
摘要翻译：一种制造半导体封装的方法，包括：形成包括多个单元基板的带状基板，每个单元基板在单元基板的第一表面上设置有第一连接焊盘和第二连接焊盘，并且每个单元基板被电气和物理隔离通过锯线的干预，形成在各个单元基板上的第一接地连接焊盘，每个第一接地连接焊盘与相应的单元基板上的第一连接焊盘电耦合，形成在锯上的第二接地连接焊盘在单元基板的第一表面侧上并且与单元基板电隔离，以及形成在锯线上的测试布线，测试布线与单元基板电隔离并与第二接地连接焊盘电耦合; 以及将半导体芯片附接到各个单元基板上。

3. 发明授权

US09252136B2 Package stacked device 有权
标题翻译：封装堆叠设备
公开(公告)号：US09252136B2
公开(公告)日：2016-02-02
申请号：US14468885
申请日：2014-08-26
申请人： SK hynix Inc.
发明人： Seung Jee Kim , Qwan Ho Chung
IPC分类号： H01L23/02 , H01L25/11 , H01L23/498
CPC分类号： H01L25/117 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/105 , H01L2224/04105 , H01L2224/18 , H01L2224/73267
摘要： A package stacked device may include a first packaging body layer having a first chip embedded therein, and a second packaging body layer positioned under the first packaging body layer and having a second chip embedded therein. The package stacked device may also include a first connection unit protruding from a first bottom surface of the first packaging body layer, a second connection unit protruding from a second top surface of the second packaging body layer, a first covering layer providing a first opening to expose the top surface of the second connection unit and substantially covering the second top surface of the second packaging body layer, and a first adhesive layer substantially covering the exposed top surface of the second connection unit within the first opening. The first connection unit may be inserted into the first opening and connected to the first adhesive layer.
摘要翻译：封装堆叠器件可以包括其中嵌入有第一芯片的第一封装体层和位于第一封装体层之下并具有嵌入其中的第二芯片的第二封装体层。包装堆叠装置还可以包括从第一包装体层的第一底表面突出的第一连接单元，从第二包装体层的第二顶表面突出的第二连接单元，第一覆盖层，暴露第二连接单元的顶表面并且基本上覆盖第二包装体层的第二顶表面，以及基本覆盖第一开口内的第二连接单元的暴露的顶表面的第一粘合剂层。第一连接单元可插入第一开口并连接到第一粘合剂层。

4. 发明授权

US09209146B2 Electronic device packages having bumps and methods of manufacturing the same 有权
标题翻译：具有凸块的电子器件封装及其制造方法
公开(公告)号：US09209146B2
公开(公告)日：2015-12-08
申请号：US14532393
申请日：2014-11-04
申请人： SK hynix Inc.
发明人： Seung Jee Kim , Qwan Ho Chung , Jong Hyun Nam , Si Han Kim , Sang Yong Lee , Seong Cheol Shin
IPC分类号： H01L23/00 , H01L23/498 , H01L23/538 , H01L21/768 , H01L23/31 , H01L21/56
CPC分类号： H01L24/11 , H01L21/56 , H01L21/768 , H01L23/3121 , H01L23/49827 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/19 , H01L24/83 , H01L2224/02333 , H01L2224/02351 , H01L2224/02372 , H01L2224/02379 , H01L2224/03334 , H01L2224/0346 , H01L2224/03472 , H01L2224/03474 , H01L2224/03903 , H01L2224/03906 , H01L2224/0401 , H01L2224/04105 , H01L2224/05017 , H01L2224/05026 , H01L2224/05144 , H01L2224/05147 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/11334 , H01L2224/11602 , H01L2224/1184 , H01L2224/12105 , H01L2224/13022 , H01L2224/131 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.
摘要翻译：电子器件封装包括具有设置在半导体芯片的接触部分上的柱和从柱的上部侧向突出的扩大部分的凸块; 互连部分，其具有基本上围绕所述柱的扩大部分和上侧壁的锁定部分; 以及基本上围绕所述凸起和所述锁定部分的绝缘层，以将所述互连部分与所述半导体芯片分离。

5. 发明授权

US09368456B2 Semiconductor package having EMI shielding and method of fabricating the same 有权
标题翻译：具有EMI屏蔽的半导体封装及其制造方法
公开(公告)号：US09368456B2
公开(公告)日：2016-06-14
申请号：US14290572
申请日：2014-05-29
申请人： SK HYNIX INC.
发明人： Qwan Ho Chung
IPC分类号： H01L23/552 , H01L23/50 , H01L21/56 , H01L21/768 , H01L23/31 , H01L23/00
CPC分类号： H01L23/552 , H01L21/56 , H01L21/76802 , H01L23/3135 , H01L23/3164 , H01L23/50 , H01L24/97 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/48147 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/06537 , H01L2225/06562 , H01L2924/12042 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a dielectric layer in which a chip is embedded, interconnection parts disposed on a first surface of the dielectric layer, through connectors each of which penetrates a portion of the dielectric layer over the chip to electrically couple the chip to a corresponding one of the interconnection parts, a shielding plate covering a second surface of the dielectric layer that is opposite to the first surface, and a shielding encapsulation part connected to one of the interconnection parts and covering sidewalls of the dielectric layer. The shielding encapsulation part includes a portion contacting the shielding plate.
摘要翻译：半导体封装包括其中嵌入有芯片的介电层，布置在电介质层的第一表面上的互连部件，通过连接器，每个连接器穿过芯片上的电介质层的一部分以将芯片电耦合到相应的一个的互连部件，覆盖与第一表面相对的电介质层的第二表面的屏蔽板和连接到互连部件中的一个并覆盖电介质层的侧壁的屏蔽封装部分。屏蔽封装部分包括接触屏蔽板的部分。

6. 发明授权

US09111820B2 Embedded package and method for manufacturing the same 有权
标题翻译：嵌入式封装及其制造方法
公开(公告)号：US09111820B2
公开(公告)日：2015-08-18
申请号：US14217624
申请日：2014-03-18
申请人： SK hynix Inc.
发明人： Qwan Ho Chung
IPC分类号： H01L23/498 , H01L23/48 , H01L21/56 , H01L23/00 , H01L23/31
CPC分类号： H01L24/14 , H01L23/3128 , H01L24/19 , H01L24/20 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2224/92144 , H01L2924/01029 , H01L2924/12042 , H01L2924/15311 , H01L2924/00
摘要： An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the to semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump.
摘要翻译：嵌入式封装包括分为单元区域和外围区域的半导体芯片，具有第一表面和远离第一表面的第二表面，并且包括形成在第一表面上的单元区域中的集成电路，形成在第一表面的周边区域中的接合焊盘和形成在接合焊盘上的凸块; 芯层，附着到所述半导体芯片的所述第二表面; 绝缘部件，其形成在包括所述半导体芯片的所述芯层上方，并且具有暴露所述凸块的开口; 以及电路布线，形成在所述绝缘部件和所述凸块上并且电连接到所述凸块，其中形成在所述电池区域中的所述绝缘部件的厚度大于所述凸块的高度。

7. 发明授权

US09609742B2 Electrical characteristics of package substrates and semiconductor packages including the same 有权
公开(公告)号：US09609742B2
公开(公告)日：2017-03-28
申请号：US14014652
申请日：2013-08-30
申请人： SK hynix Inc.
发明人： Eul Chul Jang , Qwan Ho Chung , Sang Joon Lim , Sung Woo Han
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H05K1/02 , H01L23/498 , H01L23/552
CPC分类号： H05K1/0224 , H01L23/49838 , H01L23/552 , H01L2924/0002 , H05K1/0219 , H05K1/0253 , H05K2201/09236 , H05K2201/093 , H05K2201/09345 , H05K2201/09681 , H05K2201/097 , H05K2201/09727 , H01L2924/00
摘要： Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided.

8. 发明授权

US09209150B2 Embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same 有权
标题翻译：嵌入式封装，其制造方法，包括该封装的电子系统和包括该封装的存储卡
公开(公告)号：US09209150B2
公开(公告)日：2015-12-08
申请号：US14085357
申请日：2013-11-20
申请人： SK hynix Inc.
发明人： Sang Yong Lee , Qwan Ho Chung , Seung Jee Kim , Jong Hyun Nam , Si Han Kim
IPC分类号： H01L23/48 , H01L23/00
CPC分类号： H01L24/25 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/8203 , H01L2224/92244 , H01L2924/12042 , H01L2924/00
摘要： Embedded packages are provided. The embedded package includes a chip attached to a first surface of a core layer, a plurality of bumps on a surface of the chip opposite to the core layer, and a first insulation layer surrounding the core layer, the chip and the plurality of bumps. The first insulation layer has a trench disposed in a portion of the first insulation layer to expose the plurality of bumps.
摘要翻译：提供嵌入式软件包。嵌入式封装包括附着到芯层的第一表面的芯片，与芯层相对的芯片表面上的多个凸起，以及围绕芯层，芯片和多个凸块的第一绝缘层。第一绝缘层具有设置在第一绝缘层的一部分中以暴露多个凸块的沟槽。

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