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1. 发明授权

US09859014B2 Semiconductor memory device including multi-level cell and programming method thereof 有权
公开(公告)号：US09859014B2
公开(公告)日：2018-01-02
申请号：US15212559
申请日：2016-07-18
申请人： SK hynix Inc.
发明人： Min Sang Park , Sung Ho Kim , Kyong Taek Lee , Yun Bong Lee , Gil Bok Choi
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454
摘要： There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.

2. 发明授权

US10984869B2 Memory device, memory system including the memory device, and operating method of the memory system 有权
公开(公告)号：US10984869B2
公开(公告)日：2021-04-20
申请号：US16667782
申请日：2019-10-29
申请人： SK hynix Inc.
发明人： Sung Ho Kim , Jong Han Ahn , Seong Cheon Yu
IPC分类号： G11C16/10 , G11C16/04
摘要： A memory device includes: a memory block including a plurality of main pages and a dummy page; a peripheral circuit for performing a normal program operation on the plurality of main pages and a dummy program operation on the dummy page in a program operation, and reading data stored in the dummy page and the plurality of main pages in a read operation; and control logic for controlling the peripheral circuit to program, to the dummy page, the same data as first logical page data of a first main page among the plurality of main pages in the program operation.

3. 发明授权

US10146442B2 Control logic, semiconductor memory device, and operating method 有权
公开(公告)号：US10146442B2
公开(公告)日：2018-12-04
申请号：US15642606
申请日：2017-07-06
申请人： SK hynix Inc.
发明人： Sung Ho Kim , Min Sang Park , Yong Seok Suh , Kyong Taek Lee , Gil Bok Choi
IPC分类号： G06F3/06
摘要： Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.

4. 发明授权

US09336840B2 Semiconductor apparatus capable of compensating for data output time and method for controlling the same 有权
标题翻译：能够补偿数据输出时间的半导体装置及其控制方法
公开(公告)号：US09336840B2
公开(公告)日：2016-05-10
申请号：US14536011
申请日：2014-11-07
申请人： SK hynix Inc.
发明人： Sung Ho Kim
IPC分类号： G11C7/00 , G11C7/22 , G11C5/14
CPC分类号： G11C7/22 , G11C5/14 , G11C5/147 , G11C7/1066 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor apparatus may include a base die and a plurality of core dies stacked above the base die. Each of the core dies may be configured to output a strobe signal in response to a read command, and the base die may be configured to make remaining data output times correspond to any one data output time among respective data output times of the plurality of core dies, in response to the read command and the strobe signal.
摘要翻译：半导体装置可以包括基模和堆叠在基模上方的多个芯模。每个核芯管芯可以被配置为响应于读取命令输出选通信号，并且基准管芯可以被配置为使得剩余数据输出时间对应于多个核心的各个数据输出时间中的任何一个数据输出时间响应于读取命令和选通信号而死亡。

5. 发明授权

US11029886B2 Memory system and method of operating memory system 有权
公开(公告)号：US11029886B2
公开(公告)日：2021-06-08
申请号：US16666220
申请日：2019-10-28
申请人： SK hynix Inc.
发明人： Min Ho Her , Sung Ho Kim , Seung Il Kim , Jae Min Lee
IPC分类号： G06F3/06
摘要： The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of memory blocks, the memory device configure to perform on each of the plurality of memory blocks at least one of a program operation, a read operation, or an erase operation in response to an internal command; and a controller in communication with a host and the memory device and configured to receive a request from the host and generate the internal command in response to the request from the host, the controller further configured to control the memory device to perform a stress check operation on a first memory block of the plurality of memory blocks in which the program operation has been completed.

6. 发明授权

US10296226B2 Control logic, semiconductor memory device, and operating method 有权
公开(公告)号：US10296226B2
公开(公告)日：2019-05-21
申请号：US16177109
申请日：2018-10-31
申请人： SK hynix Inc.
发明人： Sung Ho Kim , Min Sang Park , Yong Seok Suh , Kyong Taek Lee , Gil Bok Choi
IPC分类号： G06F3/06 , G11C16/16 , G11C16/30 , G11C16/10 , G11C16/04
摘要： Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.

7. 发明授权

US10224102B2 Semiconductor memory device and operation method thereof 有权
公开(公告)号：US10224102B2
公开(公告)日：2019-03-05
申请号：US15835898
申请日：2017-12-08
申请人： SK hynix Inc.
发明人： Gil Bok Choi , Sung Hoon Cho , Sung Ho Kim , Min Sang Park , Kyong Taek Lee , Myoung Kwan Cho
IPC分类号： G11C16/04 , G11C16/10
摘要： A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.

8. 发明授权

US11169741B2 Storage device and method of operating the same 有权
公开(公告)号：US11169741B2
公开(公告)日：2021-11-09
申请号：US16784117
申请日：2020-02-06
申请人： SK hynix Inc.
发明人： Min Ho Her , Sung Ho Kim , Seung Il Kim , Jae Min Lee
IPC分类号： G06F3/00 , G06F3/06 , G11C15/04 , G11C16/04
摘要： The present technology relates to a storage device and a method of operating the same. The storage device includes a memory controller configured to generate and output a get parameter command set, including normal addresses and a dummy address, during a parameter read operation, and a memory device configured to, in response to the get parameter command set, read parameter data that is stored in a CAM block and store the read parameter data in target registers corresponding to the normal addresses. The memory device stores dummy data in a dummy register corresponding to the dummy address.

9. 发明申请

US20210026564A1 MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM 有权
公开(公告)号：US20210026564A1
公开(公告)日：2021-01-28
申请号：US16666220
申请日：2019-10-28
申请人： SK hynix Inc.
发明人： Min Ho Her , Sung Ho Kim , Seung Il Kim , Jae Min Lee
IPC分类号： G06F3/06
摘要： The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of memory blocks, the memory device configure to perform on each of the plurality of memory blocks at least one of a program operation, a read operation, or an erase operation in response to an internal command; and a controller in communication with a host and the memory device and configured to receive a request from the host and generate the internal command in response to the request from the host, the controller further configured to control the memory device to perform a stress check operation on a first memory block of the plurality of memory blocks in which the program operation has been completed.

10. 发明授权

US09576668B2 Semiconductor device and operating method thereof 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US09576668B2
公开(公告)日：2017-02-21
申请号：US14970755
申请日：2015-12-16
申请人： SK hynix Inc.
发明人： Sung Ho Kim , Min Sang Park , Kyong Taek Lee
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： The semiconductor device includes a memory block including programmed pages and non-programmed pages, a peripheral circuit configured to perform a read operation of the memory block, and a control circuit configured to control the peripheral circuit so that a read voltage is applied to a word line coupled to a selected page among the pages for the read operation, a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation, and a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation.
摘要翻译：该半导体器件包括一个包括编程页面和非编程页面的存储器块，被配置为执行该存储器块的读取操作的外围电路以及一个控制电路，该控制电路被配置为控制该外围电路，使得读取电压被施加到一个字线耦合到用于读取操作的页面中的所选页面，第一通过电压被施加到与未被选择用于读取操作的页面之中的编程页面耦合的字线，以及低于第一通过电压的第二通过电压被应用于在未被选择用于读取操作的页面中耦合到非编程页面的字线。

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