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1. 发明授权

US11630721B2 Memory system and operating method thereof 有权
公开(公告)号：US11630721B2
公开(公告)日：2023-04-18
申请号：US16867660
申请日：2020-05-06
申请人： SK hynix Inc.
发明人： Tae-Hoon Kim
IPC分类号： G11C16/10 , G06F11/10 , G06F11/14 , G06F11/16 , H03M13/09
摘要： A memory system includes a controller configured to transfer first data for a program operation, and a memory device configured to perform an error check operation for determining whether second data received from the controller are equal to the first data and the program operation for storing the first data.

2. 发明授权

US10861503B1 Electronic device 有权
公开(公告)号：US10861503B1
公开(公告)日：2020-12-08
申请号：US16698802
申请日：2019-11-27
申请人： SK hynix Inc.
发明人： Myoung-Sub Kim , Tae-Hoon Kim , Hye-Jung Choi , Seok-Man Hong
IPC分类号： G11C5/02 , H01L27/22 , G11C13/00 , H01L27/108
摘要： A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.

3. 发明授权

US10783981B1 Semiconductor memory capable of reducing an initial turn-on voltage of a memory cell using a stress pulse in a test mode, and method for driving the same 有权
公开(公告)号：US10783981B1
公开(公告)日：2020-09-22
申请号：US15945620
申请日：2018-04-04
申请人： SK hynix Inc.
发明人： Sang-Hyun Ban , Tae-Hoon Kim , Woo-Tae Lee , Hye-Jung Choi
IPC分类号： G11C29/50 , H01L27/22 , G11C11/16 , H01L45/00 , H01L43/08 , H01L27/24 , G11C13/00 , G06F12/0802 , H01L23/528 , G11C29/04 , H01L43/10 , H01F10/32
摘要： An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the first lines and the second lines and coupled between the first lines and the second lines, the plurality of memory cells having a first turn-on voltage; and a test circuit block suitable for applying a stress pulse having a voltage level equal to or higher than the first turn-on voltage to one or more first lines selected from the first lines in a test mode.

4. 发明授权

US10757356B2 Comparison device and CMOS image sensor including the same 有权
公开(公告)号：US10757356B2
公开(公告)日：2020-08-25
申请号：US16219246
申请日：2018-12-13
申请人： SK hynix Inc.
发明人： Hyeon-June Kim , Tae-Hoon Kim , Hyun-Mook Park
IPC分类号： H04N5/3745 , H04N5/378 , H01L27/146 , H04N5/357 , H04N9/04 , H04N5/376
摘要： Provided are a comparison device that may minimize an influence of banding noise by offsetting the banding noise, and a CMOS image sensor including the comparison device. The comparison device may include a comparison circuit configured to compare a pixel signal and a ramp signal with each other and output a comparison signal, a banding noise adjustment circuit coupled to the comparison circuit to adjust electrical characteristic values of the comparison circuit, a banding value generation circuit coupled to the banding noise adjustment circuit to provide the banding noise adjustment circuit with a banding value generated based on a setting code value, and a banding noise reduction circuit coupled to the banding noise adjustment circuit and configured to reduce the banding noise of the comparison circuit by adjusting electrical characteristic values of the comparison circuit.

5. 发明授权

US10574917B2 Pixel output level control device and CMOS image sensor using the same 有权
公开(公告)号：US10574917B2
公开(公告)日：2020-02-25
申请号：US16401846
申请日：2019-05-02
申请人： SK hynix Inc.
发明人： Tae-Hoon Kim , Woong-Hee Lee
IPC分类号： H04N5/3745 , H04N5/378 , H04N5/369 , H04N5/376 , H04N5/365
摘要： A pixel output level control device may include: a pixel output level control unit suitable for controlling a pixel output level of a pixel signal of a pixel for reducing the time required for settling the pixel signal during a specific period; and a pixel output level retention unit suitable for maintaining the pixel output level of the pixel signal during the specific period to a fixed value, according to control of the pixel output level control unit.

6. 发明授权

US10224355B2 Comparator for low-banding noise and CMOS image sensor including the same 有权
公开(公告)号：US10224355B2
公开(公告)日：2019-03-05
申请号：US15902584
申请日：2018-02-22
申请人： SK hynix Inc.
发明人： Hyeon-June Kim , Tae-Hoon Kim
IPC分类号： H03M1/34 , H01L27/146 , H04N5/378 , H04N5/374 , H04N5/363 , H03M1/00 , H04N5/243
摘要： A comparator may include: a comparison block suitable for comparing a ramp signal and a pixel signal and outputting a comparison signal; and a gain acquisition and noise reduction block suitable for amplifying the comparison signal outputted from the comparison block to acquire a gain and reduce an occurrence of noise.

7. 发明授权

US10205897B2 Image sensor and method for driving unit pixel of image sensor 有权
公开(公告)号：US10205897B2
公开(公告)日：2019-02-12
申请号：US15251817
申请日：2016-08-30
申请人： SK hynix Inc.
发明人： JIn-Seon Kim , Woong-Hee Lee , Tae-Hoon Kim
IPC分类号： H04N5/359 , H04N5/374 , H04N5/378 , H01L27/146
摘要： A method of driving a unit pixel may include activating a transfer signal prior to an activation of a reset signal to boost a floating diffusion node of the unit pixel, during a first section of a photodiode reset period; and activating a reset signal using a hard reset, during a second section of the photodiode reset period.

8. 发明授权

US09225175B2 Power voltage selection device 有权
标题翻译：电源电压选择装置
公开(公告)号：US09225175B2
公开(公告)日：2015-12-29
申请号：US13716458
申请日：2012-12-17
申请人： SK hynix Inc.
发明人： Tae-Hoon Kim
IPC分类号： H02J1/00 , H02J4/00 , H01L27/088 , G06F1/26 , H03K17/693
CPC分类号： H02J4/00 , G06F1/263 , H01L27/088 , H03K17/693 , Y10T307/658
摘要： A power voltage selection device includes a first power voltage and a second power voltage; a power selection unit having a first PMOS transistor and a second PMOS transistor, wherein the first power voltage is supplied to a source of the first PMOS transistor, a gate of the first PMOS transistor receives a first enable signal, the second power voltage is supplied to a source of the second PMOS transistor, a gate of the second PMOS transistor receives a second enable signal, and a body of the first PMOS transistor is coupled to a body of the second PMOS transistor; an output unit having a common node to which a drain of the first PMOS transistor and a drain of the second PMOS transistor are commonly coupled; and a body voltage control unit controlling to supply one of the first power voltage and the second power voltage to the bodies of the first PMOS transistor and the second PMOS transistor, wherein the one has a higher voltage level than the other.
摘要翻译：电源电压选择装置包括第一电源电压和第二电源电压; 具有第一PMOS晶体管和第二PMOS晶体管的功率选择单元，其中所述第一电源电压被提供给所述第一PMOS晶体管的源极，所述第一PMOS晶体管的栅极接收第一使能信号，提供所述第二电源电压到第二PMOS晶体管的源极，第二PMOS晶体管的栅极接收第二使能信号，并且第一PMOS晶体管的主体耦合到第二PMOS晶体管的主体; 输出单元，具有公共节点，第一PMOS晶体管的漏极和第二PMOS晶体管的漏极共同耦合到该公共节点; 以及体电压控制单元，其控制将所述第一电源电压和所述第二电力电压中的一个提供给所述第一PMOS晶体管和所述第二PMOS晶体管的主体，其中所述第一电源电压和所述第二电源电压具有比另一个更高的电压电平。

9. 发明授权

US10685733B2 Electronic device for changing short-type defective memory cell to open-type defective memory cell by applying stress pulse 有权
公开(公告)号：US10685733B2
公开(公告)日：2020-06-16
申请号：US15854587
申请日：2017-12-26
申请人： SK hynix Inc.
发明人： Sang-Hyun Ban , Tae-Hoon Kim , Woo-Tae Lee , Hye-Jung Choi
IPC分类号： G11C29/00 , G11C29/50 , G06F1/24 , G11C29/46 , G11C29/12
摘要： Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.

10. 发明授权

US10417082B2 Memory systems and operating method thereof 有权
公开(公告)号：US10417082B2
公开(公告)日：2019-09-17
申请号：US15826857
申请日：2017-11-30
申请人： SK hynix Inc.
发明人： Tae-Hoon Kim
IPC分类号： G06F11/07 , G06F11/10
摘要： A memory system comprising: a memory device including a plurality of memory dies each having a plurality of the memory blocks; and a controller suitable for performing a command operation to the memory dies, wherein the memory device comprises means for performing an error check operation to a first data provided from the controller to store the first data the memory device.

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