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1. 发明授权

US11575254B2 Overvoltage protection circuit for a PMOS based switch 有权
公开(公告)号：US11575254B2
公开(公告)日：2023-02-07
申请号：US17095652
申请日：2020-11-11
申请人： STMicroelectronics International N.V. , STMicroelectronics (Rousset) SAS
发明人： Manoj Kumar , Ravinder Kumar , Nicolas Demange
IPC分类号： H02H3/20 , H02H1/00
摘要： An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

2. 发明授权

US11550749B2 Serial data interface with reduced loop delay 有权
公开(公告)号：US11550749B2
公开(公告)日：2023-01-10
申请号：US17143679
申请日：2021-01-07
申请人： STMicroelectronics International N.V. , STMicroelectronics (Rousset) SAS
发明人： Manoj Kumar , Kailash Kumar , Nicolas Demange
IPC分类号： G06F13/42 , G06F1/06
摘要： A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.

3. 发明申请

US20140365987A1 INPUT/OUTPUT CELL DESIGN FOR THIN GATE OXIDE TRANSISTORS WITH RESTRICTED POLY GATE ORIENTATION 有权
标题翻译：输入/输出电池设计用于具有限制聚合物栅极定向的薄栅氧化物晶体管
公开(公告)号：US20140365987A1
公开(公告)日：2014-12-11
申请号：US13911224
申请日：2013-06-06
申请人： STMicroelectronics International N.V. , STMicroelectronics (Crolles 2) SAS
发明人： Manoj Kumar , Jean Guillorit , Navin Kumar Dayani
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An input/output circuit layout has a first section in which first transistors having a thicker gate oxide are located and a second section in which second transistors having a thinner gate oxide are located. Due to process technology constraints, the gates of all of the second transistors are oriented in a single common direction. The second section has a perimeter having a square shape including a first edge and a second edge adjacent to the first edge. First connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to the first edge. Second connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to said second edge. The square shape and presence of pins on adjacent first and second edges permits rotation of the second section to fit within different orientations of the layout.
摘要翻译：输入/输出电路布局具有第一部分，其中具有较厚栅极氧化物的第一晶体管位于其中，第二部分中具有较薄栅极氧化物的第二晶体管位于其中。由于工艺技术的限制，所有第二晶体管的栅极定向在单一的共同方向。第二部分具有包括与第一边缘相邻的第一边缘和第二边缘的正方形形状的周边。耦合到第二晶体管的第一连接引脚具有从第一边缘向内并垂直于第一边缘延伸的取向。耦合到第二晶体管的第二连接引脚具有从所述第二边缘向内并垂直于所述第二边缘延伸的取向。在相邻的第一和第二边缘上的方形形状和销的存在允许第二部分的旋转以适应布局的不同取向。

4. 发明授权

US11454669B2 Circuit for detecting damage to a peripheral edge on an integrated circuit die 有权
公开(公告)号：US11454669B2
公开(公告)日：2022-09-27
申请号：US16680114
申请日：2019-11-11
申请人： STMicroelectronics International N.V. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS
发明人： Manoj Kumar , Lionel Courau , Geeta , Olivier Le-Briz
IPC分类号： G01R31/28 , H05K1/02 , H01L21/66 , H01L23/525
摘要： An integrated circuit die has a peripheral edge and a seal ring extending along the peripheral edge and surrounding a functional integrated circuit area. A test logic circuit located within the functional integrated circuit area generates a serial input data signal for application to a first end of a sensing conductive wire line extending around the seal ring between the seal ring and the peripheral edge of the integrated circuit die. Propagation of the serial input data signal along the sensing conductive wire line produces a serial output data signal at a second end of the sensing conductive wire line. The test logic circuit compares data patterns of the serial input data signal and serial output data signal to detect damage at the peripheral edge of the integrated circuit die.

5. 发明授权

US09075947B2 Input/output cell design for thin gate oxide transistors with restricted poly gate orientation 有权
标题翻译：具有限制多门取向的薄栅氧化物晶体管的输入/输出单元设计
公开(公告)号：US09075947B2
公开(公告)日：2015-07-07
申请号：US13911224
申请日：2013-06-06
申请人： STMicroelectronics (Crolles 2) SAS , STMicroelectronics International N.V.
发明人： Manoj Kumar , Jean Guillorit , Navin Kumar Dayani
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An input/output circuit layout has a first section in which first transistors having a thicker gate oxide are located and a second section in which second transistors having a thinner gate oxide are located. Due to process technology constraints, the gates of all of the second transistors are oriented in a single common direction. The second section has a perimeter having a square shape including a first edge and a second edge adjacent to the first edge. First connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to the first edge. Second connection pins coupled to the second transistors are provided with an orientation that extends inwardly from and perpendicular to said second edge. The square shape and presence of pins on adjacent first and second edges permits rotation of the second section to fit within different orientations of the layout.
摘要翻译：输入/输出电路布局具有第一部分，其中具有较厚栅极氧化物的第一晶体管位于其中，第二部分中具有较薄栅极氧化物的第二晶体管位于其中。由于工艺技术的限制，所有第二晶体管的栅极定向在单一的共同方向。第二部分具有包括与第一边缘相邻的第一边缘和第二边缘的正方形形状的周边。耦合到第二晶体管的第一连接引脚具有从第一边缘向内并垂直于第一边缘延伸的取向。耦合到第二晶体管的第二连接引脚具有从所述第二边缘向内并垂直于所述第二边缘延伸的取向。在相邻的第一和第二边缘上的方形形状和销的存在允许第二部分的旋转以适应布局的不同取向。

6. 发明授权

US11223345B2 Low power input receiver using a Schmitt trigger circuit 有权
公开(公告)号：US11223345B2
公开(公告)日：2022-01-11
申请号：US17328525
申请日：2021-05-24
申请人： STMicroelectronics International N.V.
发明人： Manoj Kumar
IPC分类号： H03K3/037
摘要： An input signal having a logic low level at a first voltage and a logic high level at a second voltage is received by a Schmitt trigger. A voltage generator outputs a reference voltage generated from a third voltage that is higher than the second voltage. A first transistor coupled between the third voltage and a power supply node of the Schmitt trigger is biased by the reference voltage to apply a fourth voltage to the power supply node of the Schmitt trigger that is dependent on the reference voltage. The reference voltage has a value which causes the fourth voltage to be less than or equal to the second voltage. A second transistor coupled between the input signal and the input of the Schmitt trigger circuit is also biased by the reference voltage to control the logic high level voltage of the input signal at the Schmitt trigger.

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