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1. 发明申请

US20130301348A1 ROW DECODER CIRCUIT FOR A PHASE CHANGE NON-VOLATILE MEMORY DEVICE 有权
标题翻译：相位变化非易失性存储器件的ROW解码器电路
公开(公告)号：US20130301348A1
公开(公告)日：2013-11-14
申请号：US13888593
申请日：2013-05-07
申请人： STMICROELECTRONICS S.R.L.
发明人： Maurizio Francesco Perroni , Guido Desandre , Salvatore Polizzi , Giuseppe Castagna
IPC分类号： G11C13/00
CPC分类号： G11C13/0028 , G11C8/10 , G11C13/0004 , G11C13/0069 , G11C2213/79
摘要： A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.
摘要翻译：用于相变非易失性存储器件的行解码器电路可以包括以字线布置的存储器单元。该装置可以被配置为接收高于第一电源电压的第一电源电压和第二电源电压。行解码器可以包括全局预解码级，其被配置为接收地址信号并且在第二电源电压的范围内产生高电压解码的地址信号，并且基于操作具有基于值的偏置信号。行解码器可以包括耦合到全局预编码阶段的行解码器级。行解码器级可以包括：选择驱动单元，被配置为基于高电压解码的地址信号产生块地址信号;以及行驱动单元，被配置为基于块地址生成用于偏置字线的行驱动信号信号和偏置信号。

2. 发明授权

US08982612B2 Row decoder circuit for a phase change non-volatile memory device 有权
标题翻译：行解码电路用于相变非易失性存储器件
公开(公告)号：US08982612B2
公开(公告)日：2015-03-17
申请号：US13888593
申请日：2013-05-07
申请人： STMicroelectronics S.r.l.
发明人： Maurizio Francesco Perroni , Guido Desandre , Salvatore Polizzi , Giuseppe Castagna
IPC分类号： G11C11/00 , G11C13/00 , G11C8/10
CPC分类号： G11C13/0028 , G11C8/10 , G11C13/0004 , G11C13/0069 , G11C2213/79
摘要： A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.
摘要翻译：用于相变非易失性存储器件的行解码器电路可以包括以字线布置的存储器单元。该装置可以被配置为接收高于第一电源电压的第一电源电压和第二电源电压。行解码器可以包括全局预解码级，其被配置为接收地址信号并且在第二电源电压的范围内产生高电压解码的地址信号，并且基于操作具有基于值的偏置信号。行解码器可以包括耦合到全局预编码阶段的行解码器级。行解码器级可以包括：选择驱动单元，被配置为基于高电压解码的地址信号产生块地址信号;以及行驱动单元，被配置为基于块地址生成用于偏置字线的行驱动信号信号和偏置信号。

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