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1. 发明申请

US20130122669A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20130122669A1
公开(公告)日：2013-05-16
申请号：US13676717
申请日：2012-11-14
申请人： Sumitomo Electric Device Innovations, Inc.
发明人： Masatoshi Koyama , Kazuaki Matsuura , Tsutomu Komatani
IPC分类号： H01L29/66 , H01L21/02
CPC分类号： H01L29/0611 , H01L21/02104 , H01L21/02107 , H01L21/0217 , H01L21/31116 , H01L29/0649 , H01L29/0692 , H01L29/2003 , H01L29/41758 , H01L29/66045 , H01L29/66462 , H01L29/66568 , H01L29/7786
摘要： A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.

2. 发明授权

US09299770B2 Method for manufacturing semiconductor device 有权
公开(公告)号：US09299770B2
公开(公告)日：2016-03-29
申请号：US14696007
申请日：2015-04-24
申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
发明人： Masatoshi Koyama , Kazuaki Matsuura , Tsutomu Komatani
IPC分类号： H01L21/302 , H01L29/06 , H01L29/66 , H01L21/02 , H01L29/778 , H01L21/311 , H01L29/20 , H01L29/417
CPC分类号： H01L29/0611 , H01L21/02104 , H01L21/02107 , H01L21/0217 , H01L21/31116 , H01L29/0649 , H01L29/0692 , H01L29/2003 , H01L29/41758 , H01L29/66045 , H01L29/66462 , H01L29/66568 , H01L29/7786
摘要： A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.

3. 发明授权

US09991160B2 Process of forming semiconductor device having interconnection formed by electro-plating 有权
公开(公告)号：US09991160B2
公开(公告)日：2018-06-05
申请号：US15635937
申请日：2017-06-28
申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
发明人： Kazuaki Matsuura
IPC分类号： H01L29/06 , H01L21/768 , H01L21/3213 , H01L21/288
CPC分类号： H01L21/76885 , H01L21/2885 , H01L21/32136 , H01L21/32139 , H01L21/76873 , H01L29/0696
摘要： A process of forming a semiconductor device that includes an interconnection formed by electro-plating is disclosed. The process comprises steps of: forming a stopper layer on a first insulating film; covering the stopper layer and the first insulating film with a second insulating film; preparing a first mask having an edge that overlaps with the stopper layer; depositing a seed layer on the first mask and the second insulating film that is exposed from the first mask; preparing a second mask having an edge that overlaps with the stopper layer, the edge of the first mask being retreated from the edge of the second mask; forming an upper layer on the seed layer by electro-plating a metal so as not to overlap with the first mask; and removing the seed layer exposed from the upper layer by etching.

4. 发明申请

US20150228715A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150228715A1
公开(公告)日：2015-08-13
申请号：US14696007
申请日：2015-04-24
申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
发明人： Masatoshi Koyama , Kazuaki Matsuura , Tsutomu Komatani
IPC分类号： H01L29/06 , H01L21/311 , H01L29/66
CPC分类号： H01L29/0611 , H01L21/02104 , H01L21/02107 , H01L21/0217 , H01L21/31116 , H01L29/0649 , H01L29/0692 , H01L29/2003 , H01L29/41758 , H01L29/66045 , H01L29/66462 , H01L29/66568 , H01L29/7786
摘要： A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.
摘要翻译：一种制造半导体器件的方法包括：形成第一有源区，第二有源区，位于第一有源区和第二有源区之间的非活性区，以及与第一有源区交叉的第三有源区，在半导体层中的第二有源区的第一有源区; 在半导体层上形成绝缘层; 并通过干蚀刻在绝缘层中选择性地形成开口。

5. 发明授权

US09040426B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09040426B2
公开(公告)日：2015-05-26
申请号：US13676717
申请日：2012-11-14
申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
发明人： Masatoshi Koyama , Kazuaki Matsuura , Tsutomu Komatani
IPC分类号： H01L21/302 , H01L29/66 , H01L21/02 , H01L29/778 , H01L29/06 , H01L29/20 , H01L29/417
CPC分类号： H01L29/0611 , H01L21/02104 , H01L21/02107 , H01L21/0217 , H01L21/31116 , H01L29/0649 , H01L29/0692 , H01L29/2003 , H01L29/41758 , H01L29/66045 , H01L29/66462 , H01L29/66568 , H01L29/7786
摘要： A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.
摘要翻译：一种制造半导体器件的方法包括：形成第一有源区，第二有源区，位于第一有源区和第二有源区之间的非活性区，以及与第一有源区交叉的第三有源区，在半导体层中的第二有源区的第一有源区; 在半导体层上形成绝缘层; 并通过干蚀刻在绝缘层中选择性地形成开口。

6. 发明申请

US20130288401A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20130288401A1
公开(公告)日：2013-10-31
申请号：US13872347
申请日：2013-04-29
申请人： Sumitomo Electric Device Innovations, Inc.
发明人： Kazuaki Matsuura
IPC分类号： H01L21/66
CPC分类号： H01L22/10 , H01L21/30621 , H01L21/76898 , H01L22/12 , H01L22/26 , H01L29/2003 , H01L29/4175 , H01L29/66462 , H01L29/7787
摘要： A method for fabricating a semiconductor device includes: forming a first layer and a second layer in this order on a nitride semiconductor layer on a first main surface side of a substrate, the first and second layers having one of first and second arrangements, the first arrangement having the first layer of any of Au, V and Ta and the second layer of Ni, the second arrangement having the first layer of any of Ti, TiW, Al, W, Mo, Nb, Pt, Ta and V and the second layer of Au; forming a mask on a second main surface side of the substrate, the mask having an opening; applying an etching process to the substrate and the nitride semiconductor layer exposed in the opening of the mask; and determining an endpoint of the etching process by confirming elimination of the first layer in the opening of the mask.
摘要翻译：一种制造半导体器件的方法包括：在衬底的第一主表面侧上的氮化物半导体层上依次形成第一层和第二层，第一和第二层具有第一和第二布置之一，第一和第二层具有Au，V和Ta中的任一个的第一层和第二层Ni，第二布置具有Ti，TiW，Al，W，Mo，Nb，Pt，Ta和V中的任一个的第一层，第二层具有第二层。 Au层; 在基板的第二主表面侧上形成掩模，所述掩模具有开口; 对掩模的开口中暴露的衬底和氮化物半导体层施加蚀刻工艺; 以及通过确认所述掩模的开口中的所述第一层的消除来确定所述蚀刻工艺的端点。

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