专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130311747A1 Memory Mapping and Translation for Arbitrary Number of Memory Units 有权
标题翻译：内存映射和翻译任意数量的内存单元
公开(公告)号：US20130311747A1
公开(公告)日：2013-11-21
申请号：US13472180
申请日：2012-05-15
申请人： Sailesh Kumar , William Lynch , Joji Philip , Michel Hanna
发明人： Sailesh Kumar , William Lynch , Joji Philip , Michel Hanna
IPC分类号： G06F12/10
CPC分类号： G06F12/0607 , G06F12/10
摘要： A method for address translation in a memory comprising a plurality of memory streaming units (MSUs), wherein n represents the number of MSUs and n is not a power of two, and wherein the memory further comprises a striped region, the method comprising determining an MSU from among the plurality of MSUs having a physical address (PA) in the striped region corresponding to a logical address (LA) comprising performing a modulo n operation on less than all the bits representing the LA; and transmitting the LA to the MSU.
摘要翻译：一种用于存储器中的地址转换的方法，包括多个存储器流单元（MSU），其中n表示MSU的数量，n不是2的幂，并且其中所述存储器还包括条带区域，所述方法包括：在具有对应于逻辑地址（LA）的条带区域中的具有物理地址（PA）的多个MSU中的MSU包括在小于表示LA的所有位的执行模n操作; 并将LA发送到MSU。

2. 发明授权

US09135170B2 Memory mapping and translation for arbitrary number of memory units 有权
标题翻译：内存映射和转换任意数量的内存单元
公开(公告)号：US09135170B2
公开(公告)日：2015-09-15
申请号：US13472180
申请日：2012-05-15
申请人： Sailesh Kumar , William Lynch , Joji Philip , Michel Hanna
发明人： Sailesh Kumar , William Lynch , Joji Philip , Michel Hanna
IPC分类号： G06F12/10 , G06F12/06
CPC分类号： G06F12/0607 , G06F12/10
摘要： A method for address translation in a memory comprising a plurality of memory streaming units (MSUs), wherein n represents the number of MSUs and n is not a power of two, and wherein the memory further comprises a striped region, the method comprising determining an MSU from among the plurality of MSUs having a physical address (PA) in the striped region corresponding to a logical address (LA) comprising performing a modulo n operation on less than all the bits representing the LA; and transmitting the LA to the MSU.
摘要翻译：一种用于存储器中的地址转换的方法，包括多个存储器流单元（MSU），其中n表示MSU的数量，n不是2的幂，并且其中所述存储器还包括条带区域，所述方法包括：在具有对应于逻辑地址（LA）的条带区域中的具有物理地址（PA）的多个MSU中的MSU包括在小于表示LA的所有位的执行模n操作; 并将LA发送到MSU。

3. 发明授权

US09130856B2 Creating multiple NoC layers for isolation or avoiding NoC traffic congestion 有权
标题翻译：创建多个NoC层进行隔离或避免NoC流量拥塞
公开(公告)号：US09130856B2
公开(公告)日：2015-09-08
申请号：US13752226
申请日：2013-01-28
申请人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
发明人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
IPC分类号： G01R31/08 , H04L12/803
CPC分类号： H04L47/125 , H04L45/66 , H04L47/70
摘要： Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.
摘要翻译：本文描述的系统和方法涉及基于网络片上（NoC）互连的解决方案，其基于系统业务流的带宽要求，自动且动态地确定NoC互连系统中所需的层数。通过在映射不同NoC层的信道和路由之间的业务流的负载分担来动态分配和最小化层数。可以分配附加层以提供可能需要用于死锁避免的附加虚拟通道并且维持各种系统流之间的隔离属性。可以一起执行用于附加带宽和附加虚拟通道（VC）的层分配。

4. 发明申请

US20170063693A1 HETEROGENEOUS CHANNEL CAPACITIES IN AN INTERCONNECT 审中-公开
标题翻译：互连中的异构通道容量
公开(公告)号：US20170063693A1
公开(公告)日：2017-03-02
申请号：US14519639
申请日：2014-10-21
申请人： Sailesh Kumar , Joji Philip , Eric Norige , Sundari Mitra
发明人： Sailesh Kumar , Joji Philip , Eric Norige , Sundari Mitra
IPC分类号： H04L12/803 , H04L12/26
CPC分类号： H04L47/122 , H04L43/062 , H04L49/109
摘要： Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.
摘要翻译：涉及构造系统互连的系统和方法，其中不同的信道具有不同的位数宽度。本文公开了构造这种异构信道NoC互连的示例性过程，其中可以基于所提供的系统的各种组件之间的带宽和等待时间来确定信道宽度。

5. 发明授权

US09244880B2 Automatic construction of deadlock free interconnects 有权
标题翻译：自动构建无死锁互连
公开(公告)号：US09244880B2
公开(公告)日：2016-01-26
申请号：US13599559
申请日：2012-08-30
申请人： Joji Philip , Sailesh Kumar , Eric Norige , Mahmud Hassan , Sundari Mitra
发明人： Joji Philip , Sailesh Kumar , Eric Norige , Mahmud Hassan , Sundari Mitra
IPC分类号： G06F13/36 , G06F15/173 , G06F15/78 , H04L12/721
CPC分类号： G06F15/17312 , G06F15/7825 , H04L45/06
摘要： Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.
摘要翻译：描述了在多核系统中自动构建无死锁互通网络的系统和方法。这里描述的示例实施例涉及在系统的块之间的用户指定的通信模式的映射期间的死锁检测。然后通过重新分配信道资源来避免检测到的死锁。针对大规模多核芯片系统芯片上的网络片上互连提出了死锁避免方案的示例实施例。

6. 发明授权

US09185026B2 Tagging and synchronization for fairness in NOC interconnects 有权
标题翻译：标记和同步，以便在NOC互连中实现公平性
公开(公告)号：US09185026B2
公开(公告)日：2015-11-10
申请号：US13723882
申请日：2012-12-21
申请人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
发明人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
IPC分类号： H04L12/721 , H04L12/851 , H04L12/933 , H04L12/947
CPC分类号： H04L45/44 , H04L47/24 , H04L49/109 , H04L49/25
摘要： Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve tagging the messages with meta-information when the messages are injected in the interconnection network. Example implementations may involve routers using various arbitration phases, and making local arbitration decisions based on the meta-information of incoming messages. The meta-information can be of various types based on the number of router arbitration phases, and the desired level of sophistication.
摘要翻译：本文所述的系统和方法针对NoC互连的解决方案，其提供各种竞争者之间的资源带宽的端到端均匀和加权公平分配。示例实现是完全分布的，并且当消息被注入到互连网络中时，涉及使用元信息来标记消息。示例性实现可以涉及使用各种仲裁阶段的路由器，并且基于进入消息的元信息进行本地仲裁决定。基于路由器仲裁阶段的数量和所需的复杂程度，元信息可以是各种类型的。

7. 发明申请

US20140211622A1 CREATING MULTIPLE NOC LAYERS FOR ISOLATION OR AVOIDING NOC TRAFFIC CONGESTION 有权
标题翻译：创建多个NOC层以隔离或避免NOC交通堵塞
公开(公告)号：US20140211622A1
公开(公告)日：2014-07-31
申请号：US13752226
申请日：2013-01-28
申请人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
发明人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
IPC分类号： H04L12/56
CPC分类号： H04L47/125 , H04L45/66 , H04L47/70
摘要： Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.
摘要翻译：本文描述的系统和方法涉及基于网络片上（NoC）互连的解决方案，其基于系统业务流的带宽要求，自动且动态地确定NoC互连系统中所需的层数。通过在映射不同NoC层的信道和路由之间的业务流的负载分担来动态分配和最小化层数。可以分配附加层以提供可能需要用于死锁避免的附加虚拟通道并且维持各种系统流之间的隔离属性。可以一起执行用于附加带宽和附加虚拟通道（VC）的层分配。

8. 发明授权

US09253085B2 Hierarchical asymmetric mesh with virtual routers 有权
标题翻译：虚拟路由器的层次化非对称网格
公开(公告)号：US09253085B2
公开(公告)日：2016-02-02
申请号：US13723732
申请日：2012-12-21
申请人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
发明人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
IPC分类号： H04L12/775 , H04L12/715
CPC分类号： H04L45/58 , H04L45/04
摘要： A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.
摘要翻译：片上网络配置包括以二维网格布置的第一多个核心; 第一多个路由器，所述第一多个路由器中的每一个与所述第一多个核中的相应的本地路由器相关联，所述第一多个路由器中的每一个具有多个定向端口，所述多个定向端口被配置为提供到所述第一多个核心中的其他核心的路由器设置在所述二维网状布置的周围的第二多个芯; 以及第二多个路由器，所述第二多个路由器中的每一个与所述第二多个核中的对应的本地核心相关联，并且具有被配置为提供到所述第一多个路由器中的相邻路由器的连接的定向端口。

9. 发明授权

US09007920B2 QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes 有权
标题翻译：通过向NoC节点信道分配权重并在NoC节点使用加权仲裁，在异构NoC中进行QoS
公开(公告)号：US09007920B2
公开(公告)日：2015-04-14
申请号：US13745696
申请日：2013-01-18
申请人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
发明人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
IPC分类号： H04L5/00 , H04L12/725
CPC分类号： H04L5/0035 , H04L45/302
摘要： Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations.
摘要翻译：本文所述的系统和方法针对NoC互连的解决方案，其提供各种竞争者之间的资源带宽的端到端均匀和加权公平分配。示例实现是完全分布的，并且涉及基于在信道上的流的带宽要求的基于片上网络（NoC）中的各种信道的计算权重。示例性实现可以涉及使用权重来在NoC中的信道之间执行加权仲裁以提供服务质量（QoS）。可以通过监测通道上的流动的活动来动态地调整权重。新调整的权重可用于执行加权仲裁，以避免不公平的带宽分配。

10. 发明授权

US09009648B2 Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification 有权
标题翻译：通过捕获使用高级别规范的IP内核的内部依赖关系，自动死锁检测和系统互连中的避免
公开(公告)号：US09009648B2
公开(公告)日：2015-04-14
申请号：US13745684
申请日：2013-01-18
申请人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
发明人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
IPC分类号： H04L12/26 , H04L12/801
CPC分类号： H04L47/12 , H04L45/18 , H04L49/109
摘要： Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.
摘要翻译：描述了在多核系统中自动构建无死锁互通网络的系统和方法。本文描述的示例实现涉及高级别规范以捕获各种核的内部依赖性，并且与用户指定的系统流量简档一起使用它来自动检测系统中的协议级死锁。当所有检测到的死锁被解决或者不存在这样的死锁时，系统各个核心之间的流量简档中的消息可以被自动映射到互连通道并检测网络级死锁。然后可以通过重新分配信道资源来避免检测到的死锁。内部依赖性规范的一个示例实现，并将其用于死锁避免方案，针对大规模多核系统芯片上的片上互连提出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式