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1. 发明授权

US07202149B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07202149B2
公开(公告)日：2007-04-10
申请号：US11010389
申请日：2004-12-14
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

2. 发明授权

US07714367B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07714367B2
公开(公告)日：2010-05-11
申请号：US11694467
申请日：2007-03-30
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

3. 发明申请

US20070170513A1 Semiconductor Device and Manufacturing Method Thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070170513A1
公开(公告)日：2007-07-26
申请号：US11694467
申请日：2007-03-30
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

4. 发明申请

US20050133862A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050133862A1
公开(公告)日：2005-06-23
申请号：US11010389
申请日：2004-12-14
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/76 , H01L21/3205
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露于第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

5. 发明授权

US08441021B2 Display device and manufacturing method thereof 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US08441021B2
公开(公告)日：2013-05-14
申请号：US13567215
申请日：2012-08-06
申请人： Kunio Hosoya , Saishi Fujikawa , Takahiro Kasahara
发明人： Kunio Hosoya , Saishi Fujikawa , Takahiro Kasahara
IPC分类号： H01L29/18 , H01L33/00
CPC分类号： H01L21/84 , G02F2202/105 , H01L27/3262 , H01L27/3293 , H01L29/66772 , H01L51/52
摘要： To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor substrates to form a plurality of regions each comprising a single crystal semiconductor film over the base substrate; forming a plurality of transistors each comprising the single crystal semiconductor film as a channel formation region; and forming a plurality of pixel electrodes over the region provided with the single crystal semiconductor film and a region not provided with the single crystal semiconductor film. Some of the transistors electrically connecting to the pixel electrodes formed over the region not provided with the single crystal semiconductor film are formed in the region provided with the single crystal semiconductor film.
摘要翻译：为了实现显示部分的放大和高清晰度，在像素中使用单晶半导体膜作为晶体管，并且包括以下步骤：将多个单晶半导体衬底接合到基底衬底; 分离所述多个单晶半导体衬底的一部分以在所述基底衬底上形成各自包括单晶半导体膜的多个区域; 形成各自包含所述单晶半导体膜作为沟道形成区域的多个晶体管; 以及在设置有单晶半导体膜的区域和未设置单晶半导体膜的区域上形成多个像素电极。电连接到形成在未设置单晶半导体膜的区域上的像素电极的一些晶体管形成在设置有单晶半导体膜的区域中。

6. 发明授权

US08344379B2 Display device and manufacturing method of the same 有权
公开(公告)号：US08344379B2
公开(公告)日：2013-01-01
申请号：US12565854
申请日：2009-09-24
申请人： Saishi Fujikawa , Kunio Hosoya
发明人： Saishi Fujikawa , Kunio Hosoya
IPC分类号： H01L29/04 , H01L33/00
CPC分类号： H01L51/055 , H01L27/124 , H01L27/1288 , H01L27/3279 , H01L29/4908 , H01L51/0023 , H01L51/56
摘要： A plurality of wires and electrodes are formed by forming a first conductive film, selectively forming a resist over the first conductive film, forming a second conductive film over the first conductive film and the resist, removing the second conductive film formed over the resist by removing the resist, forming a third conductive film so as to cover the second conductive film formed over the first conductive film, and selectively etching the first conductive film and the third conductive film. Thus, wires using a low resistance material can be formed in a large-sized panel, and thus, a problem of signal delay can be solved.

7. 发明申请

US20090142867A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090142867A1
公开(公告)日：2009-06-04
申请号：US12325584
申请日：2008-12-01
申请人： Saishi Fujikawa , Yoko Chiba
发明人： Saishi Fujikawa , Yoko Chiba
IPC分类号： H01L21/336 , H01L21/02
CPC分类号： H01L27/1214 , H01L27/1288
摘要： The number of photomasks is reduced in a method for manufacturing a liquid crystal display device which operates in a fringe field switching mode, whereby a manufacturing process is simplified and manufacturing cost is reduced. A first transparent conductive film and a first metal film are sequentially stacked over a light-transmitting insulating substrate; the first transparent conductive film and the first metal film are shaped using a multi-tone mask which is a first photomask; an insulating film, a first semiconductor film, a second semiconductor film, and a second metal film are sequentially stacked; the second metal film and the second semiconductor film are shaped using a multi-tone mask which is a second photomask; a protective film is formed; the protective film is shaped using a third photomask; a second transparent conductive film is formed; and the second transparent conductive film is shaped using a fourth photomask.
摘要翻译：在用于制造在边缘场切换模式下操作的液晶显示装置的方法中，光掩模的数量减少，由此简化了制造工艺并降低了制造成本。第一透明导电膜和第一金属膜依次层叠在透光绝缘基板上; 使用作为第一光掩模的多色调掩模来成形第一透明导电膜和第一金属膜; 顺序堆叠绝缘膜，第一半导体膜，第二半导体膜和第二金属膜; 使用作为第二光掩模的多色调掩模来成形第二金属膜和第二半导体膜; 形成保护膜; 保护膜使用第三光掩模成形; 形成第二透明导电膜; 并且使用第四光掩模来成形第二透明导电膜。

8. 发明申请

US20090101906A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20090101906A1
公开(公告)日：2009-04-23
申请号：US12254603
申请日：2008-10-20
申请人： Kunio HOSOYA , Saishi Fujikawa
发明人： Kunio HOSOYA , Saishi Fujikawa
IPC分类号： H01L33/00 , H01L21/00
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/41733 , H01L29/66765 , H01L29/78609 , H01L29/78678
摘要： A first resist pattern is formed by exposure using a first multi-tone photomask, and a first conductive layer, a first insulating layer, a first semiconductor layer, and a second semiconductor layer are etched, so that an island-shaped single layer and an island-shaped stack are formed. Here, sidewalls are formed on side surfaces of the island-shaped single layer and the island-shaped stack. Further, a second resist pattern is formed by exposure using a second multi-tone photomask, and a second conductive layer and the second semiconductor layer are etched, so that a thin film transistor, a pixel electrode, and a connection terminal are formed. After that, a third resist pattern is formed by exposure from a rear side using metal layers of the first conductive layer and the second conductive layer as masks, and the third insulating layer are etched, so that a protective insulating layer is formed.
摘要翻译：通过使用第一多色调光掩模的曝光形成第一抗蚀剂图案，并且蚀刻第一导电层，第一绝缘层，第一半导体层和第二半导体层，使得岛状单层和形成岛状叠层。这里，在岛状单层和岛状叠层的侧面形成有侧壁。此外，通过使用第二多色调光掩模的曝光形成第二抗蚀剂图案，并且蚀刻第二导电层和第二半导体层，从而形成薄膜晶体管，像素电极和连接端子。之后，使用第一导电层和第二导电层的金属层作为掩模从后侧曝光形成第三抗蚀剂图案，并且蚀刻第三绝缘层，从而形成保护绝缘层。

9. 发明申请

US20080079892A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080079892A1
公开(公告)日：2008-04-03
申请号：US11902554
申请日：2007-09-24
申请人： Saishi Fujikawa , Kunio Hosoya
发明人： Saishi Fujikawa , Kunio Hosoya
IPC分类号： G02F1/1339
CPC分类号： G02F1/13394 , G02F1/133512 , G02F1/1362
摘要： When a columnar spacer is provided in a region overlapping with a TFT, there is a concern that pressure will be applied when attaching a pair of substrates to each other, which may result in the TFT being adversely affected and a crack forming. A dummy layer is formed of an inorganic material below a columnar spacer which is formed in a position overlapping with the TFT. The dummy layer is located in the position overlapping with the TFT, so that pressure applied to the TFT in a step of attaching the pair of substrates is distributed and relieved. The dummy layer is preferably formed of the same material as a pixel electrode so that it is formed without an increase in the number of processing steps.
摘要翻译：当在与TFT重叠的区域中设置柱状间隔物时，担心当将一对基板彼此连接时施加压力，这可能导致TFT受到不利影响和形成裂纹。虚设层由形成在与TFT重叠的位置的柱状间隔物下方的无机材料形成。虚设层位于与TFT重叠的位置，从而在安装一对基板的步骤中施加到TFT的压力被分配和释放。虚拟层优选由与像素电极相同的材料形成，使得其形成而不增加处理步骤的数量。

10. 发明申请

US20050048744A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050048744A1
公开(公告)日：2005-03-03
申请号：US10919513
申请日：2004-08-17
申请人： Atsuo Isobe , Satoru Saito , Saishi Fujikawa
发明人： Atsuo Isobe , Satoru Saito , Saishi Fujikawa
IPC分类号： H01L21/20 , H01L21/336 , H01L29/786 , C30B1/00 , H01L21/36
CPC分类号： H01L21/02686 , H01L21/02672 , H01L21/2022 , H01L21/2026 , H01L29/66757 , H01L29/78675 , Y10S438/978
摘要： Since sodium contained in glass, or glass itself has low heat resistance; a CPU fabricated using a TFT formed over a glass substrate or the like has not been obtained. In the case of operating a CPU with high-speed, the length of a gate (gate length) of a TFT is required to be shorter. However, since a glass substrate has large deflection, a gate electrode cannot have been etched to have a gate length short enough to be used for a CPU. According to the invention, a conductive film is formed over a crystalline semiconductor film formed over a glass substrate, a mask is formed over the conductive film, and the conductive film is etched by using the mask; thus, a thin film transistor with a gate length of 1.0 μm or less is formed. In particular, the crystalline semiconductor film is formed by crystallizing an amorphous semiconductor film formed over a glass substrate by laser irradiation.
摘要翻译：由于玻璃中含有的钠或玻璃本身具有低耐热性; 没有获得使用在玻璃基板等上形成的TFT制造的CPU。在高速运行CPU的情况下，TFT的栅极长度（栅极长度）要求较短。然而，由于玻璃基板具有大的偏转，所以栅极电极不能被蚀刻以具有足够短的栅极长度以用于CPU。根据本发明，在形成在玻璃基板上的结晶半导体膜上形成导电膜，在导电膜上形成掩模，并使用掩模蚀刻导电膜; 因此，形成栅极长度为1.0μm以下的薄膜晶体管。特别地，通过激光照射使在玻璃基板上形成的非晶半导体膜结晶化而形成结晶半导体膜。

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