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    • 2. 发明授权
    • Thin film transistor array panel and method of manufacturing the same
    • 薄膜晶体管阵列面板及其制造方法
    • US09368515B2
    • 2016-06-14
    • US14070886
    • 2013-11-04
    • SAMSUNG DISPLAY CO., LTD.
    • Dong Jo KimJi Seon LeeJong Chan LeeYoon Ho KhangSang Ho ParkYong Su LeeJung Kyu Lee
    • H01L27/12
    • H01L27/1225H01L27/1214H01L27/127H01L27/1288
    • A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.
    • 薄膜晶体管阵列面板可以包括在半导体层中形成的氧化物半导体的沟道层,形成在半导体层中并连接到第一侧的沟道层的源电极,形成在半导体层中的漏电极和 连接到相对的第二侧的沟道层,形成在与漏电极的半导体层相同的部分中的半导体层中的像素电极,设置在沟道层上的绝缘层,设置在栅电极上的栅极线 绝缘层,设置在源电极和漏电极上的钝化层,像素电极和栅极线以及设置在钝化层上的数据线。 沟道层的宽度可以基本上等于像素电极在与栅极线平行的方向上的宽度。
    • 10. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME
    • 薄膜晶体管阵列及其制造方法
    • US20140175429A1
    • 2014-06-26
    • US14070886
    • 2013-11-04
    • Samsung Display Co., Ltd.
    • DONG JO KIMJi Seon LeeJong Chan LeeYoon Ho KhangSang Ho ParkYong Su LeeJung Kyu Lee
    • H01L27/12
    • H01L27/1225H01L27/1214H01L27/127H01L27/1288
    • A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.
    • 薄膜晶体管阵列面板可以包括在半导体层中形成的氧化物半导体的沟道层,形成在半导体层中并连接到第一侧的沟道层的源电极,形成在半导体层中的漏电极和 连接到相对的第二侧的沟道层,形成在与漏电极的半导体层相同的部分中的半导体层中的像素电极,设置在沟道层上的绝缘层,设置在栅电极上的栅极线 绝缘层,设置在源电极和漏电极上的钝化层,像素电极和栅极线以及设置在钝化层上的数据线。 沟道层的宽度可以基本上等于像素电极在与栅极线平行的方向上的宽度。