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1. 发明授权

US10523302B2 Apparatus and method for selecting beam pattern in communication system supporting beamforming scheme 有权
公开(公告)号：US10523302B2
公开(公告)日：2019-12-31
申请号：US15763002
申请日：2016-09-23
申请人： Samsung Electronics Co., Ltd , Korea University Research and Business Foundation
发明人： Inkyu Lee , Jong-Ho Oh , Bong-Jin Kim , Tae-Yeong Kim , Min-Ki Ahn , Tae-Seok Oh , Seok-Ju Jang
IPC分类号： H04B7/06 , H04B7/04 , H04B7/08 , H04B7/0491
摘要： The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.

2. 发明授权

US10229949B2 Via structures including etch-delay structures and semiconductor devices having via plugs 有权
公开(公告)号：US10229949B2
公开(公告)日：2019-03-12
申请号：US15625387
申请日：2017-06-16
申请人： Samsung Electronics Co., Ltd.
发明人： Byung-Jun Park , Chang-Rok Moon , Seung-Hun Shin , Seong-Ho Oh , Tae-Seok Oh , June-Taeg Lee
IPC分类号： H01L29/40 , H01L27/146 , H01L23/48 , H01L25/065 , H01L21/768
摘要： A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

3. 发明授权

US09728572B2 Via structures including etch-delay structures and semiconductor devices having via plugs 有权
公开(公告)号：US09728572B2
公开(公告)日：2017-08-08
申请号：US14561854
申请日：2014-12-05
申请人： Samsung Electronics Co., Ltd.
发明人： Byung-Jun Park , Chang-Rok Moon , Seung-Hun Shin , Seong-Ho Oh , Tae-Seok Oh , June-Taeg Lee
IPC分类号： H01L29/40 , H01L27/146 , H01L23/48 , H01L25/065 , H01L21/768
CPC分类号： H01L27/14636 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L27/14634 , H01L27/1464 , H01L27/1469 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

4. 发明授权

US10943939B2 Via structures including etch-delay structures and semiconductor devices having via plugs 有权
公开(公告)号：US10943939B2
公开(公告)日：2021-03-09
申请号：US16271917
申请日：2019-02-11
申请人： Samsung Electronics Co., Ltd.
发明人： Byung-Jun Park , Chang-Rok Moon , Seung-Hun Shin , Seong-Ho Oh , Tae-Seok Oh , June-Taeg Lee
IPC分类号： H01L29/40 , H01L27/146 , H01L23/48 , H01L25/065 , H01L21/768 , H01L25/00
摘要： A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

5. 发明授权

US09455284B2 Stack type image sensor 有权
标题翻译：堆叠式图像传感器
公开(公告)号：US09455284B2
公开(公告)日：2016-09-27
申请号：US14602427
申请日：2015-01-22
申请人： Samsung Electronics Co., Ltd.
发明人： Byung-Jun Park , Seung-Hun Shin , Chang-Rok Moon , Tae-Seok Oh , June-Taeg Lee
IPC分类号： H01L27/146
CPC分类号： H01L27/14605 , H01L21/76898 , H01L23/481 , H01L27/14612 , H01L27/1462 , H01L27/1463 , H01L27/14636 , H01L27/1464 , H01L27/14687
摘要： A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.
摘要翻译：堆叠型图像传感器可以包括：第一芯片，其包括穿过第一衬底的通孔隔离沟槽，在通孔隔离沟槽中包括绝缘材料的通孔隔离层，第一衬底上的第一导电层和第一绝缘层; 第二芯片，包括在第二基板上的第二导电层，以及与第一绝缘层接触的第二绝缘层; 穿过所述第一衬底以相对于所述沟槽暴露所述第二导电层的第一通孔沟槽; 以及形成在所述第一通孔沟槽中的第一通孔，并且包括通过所述通孔隔离层与所述第一基板绝缘的第三导电层，所述第三导电层将所述第一导电层电连接到所述第二导电层。第三导电层可以形成在通孔隔离沟槽中。

6. 发明授权

US09177987B2 Binary CMOS image sensors, methods of operating same, and image processing systems including same 有权
标题翻译：二进制CMOS图像传感器，操作方法以及包括其的图像处理系统
公开(公告)号：US09177987B2
公开(公告)日：2015-11-03
申请号：US14051179
申请日：2013-10-10
申请人： Samsung Electronics Co., Ltd.
发明人： Tae-Yon Lee , Ju Hwan Jung , Seok Yong Hong , Tae-Chan Kim , Dong Ki Min , Yoon Dong Park , Sang-Chul Sul , Tae-Seok Oh , Je Il Ryu , Kwang-Hyun Lee , Young-Gu Jin
IPC分类号： H01L27/00 , H01L27/146 , H04N5/376
CPC分类号： H01L27/14643 , H01L27/14612 , H01L27/1464 , H04N5/3765
摘要： A binary complementary metal-oxide-semiconductor (CMOS) image sensor includes a pixel array and a readout circuit. The pixel array includes at least one pixel having a plurality of sub-pixels. The readout circuit is configured to quantize a pixel signal output from the pixel using a reference signal. The pixel signal corresponds to sub-pixel signals output from sub-pixels, from among the plurality of sub-pixels, activated in response to incident light.
摘要翻译：二元互补金属氧化物半导体（CMOS）图像传感器包括像素阵列和读出电路。像素阵列包括具有多个子像素的至少一个像素。读出电路被配置为使用参考信号量化从像素输出的像素信号。像素信号对应于从子像素输出的子像素信号，从响应于入射光激活的多个子像素之中。

7. 发明申请

US20150221695A1 VIA STRUCTURES INCLUDING ETCH-DELAY STRUCTURES AND SEMICONDUCTOR DEVICES HAVING VIA PLUGS 有权
标题翻译：通过包括ET-DELAY结构的结构和通过PLUGS的半导体器件
公开(公告)号：US20150221695A1
公开(公告)日：2015-08-06
申请号：US14561854
申请日：2014-12-05
申请人： Samsung Electronics Co., Ltd.
发明人： Byung-Jun Park , Chang-Rok Moon , Seung-Hun Shin , Seong-Ho Oh , Tae-Seok Oh , June-Taeg Lee
IPC分类号： H01L27/146 , H01L25/065 , H01L23/48
CPC分类号： H01L27/14636 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L27/14634 , H01L27/1464 , H01L27/1469 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
摘要翻译：半导体器件包括下部器件和设置在下部器件上的上部器件。下部器件包括下部衬底，设置在下部衬底上的下部插头焊盘以及下部插头焊盘上的下部层间电介质层。上部器件包括上部衬底，上部衬底的下部中的蚀刻延迟结构，设置在上部衬底的底部表面上的上部焊盘，位于上部焊盘上的上层间绝缘层，以及通孔插头被配置为穿透上基板并接触上插头垫和下插头垫。通孔插头包括与上插头焊盘和第一蚀刻延迟结构接触的第一部分，以及与下插头焊盘接触的第二部分。

8. 发明申请

US20150076649A1 STACK TYPE IMAGE SENSORS AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：堆叠式图像传感器及其制造方法
公开(公告)号：US20150076649A1
公开(公告)日：2015-03-19
申请号：US14486389
申请日：2014-09-15
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-kwan KIM , Doo-Won Kwon , Jeong-ki Kim , Wook-hwan Kim , Byung-jun Park , Seung-hun Shin , June-taeg Lee , Ha-kyu Choi , Tae-Seok Oh
IPC分类号： H01L27/146
CPC分类号： H01L27/14643 , H01L24/80 , H01L27/14609 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14687 , H01L27/14689 , H01L27/1469 , H01L2224/05547 , H01L2224/08121 , H01L2224/80895 , H01L2224/80896
摘要： An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.
摘要翻译：电子器件可以包括第一半导体层，半导体层上的第一电极层，第一电极层上的粘合绝缘层，粘合绝缘层上的第二电极层，第二半导体层。第一电极层可以包括第一多个电极，第一电极层可以在粘合绝缘层和第一半导体层之间，并且粘合绝缘层可以包括SiOCN，SiBN和/或BN中的至少一种。第二电极层可以包括第二多个电极，粘合绝缘层可以在第一和第二电极层之间，并且第二电极层可以在粘合绝缘层和第二半导体层之间。

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