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1. 发明授权

US10283360B2 Semiconductor device 有权
公开(公告)号：US10283360B2
公开(公告)日：2019-05-07
申请号：US15886372
申请日：2018-02-01
申请人： Samsung Electronics Co., Ltd.
发明人： Chan Sic Yoon , Ki Seok Lee , Dong Oh Kim , Yong Jae Kim
IPC分类号： H01L21/027 , G03F1/38 , H01L21/02 , H01L27/02 , H01L27/108
摘要： Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

2. 发明授权

US10026614B2 Method for manufacturing semiconductor device 有权
公开(公告)号：US10026614B2
公开(公告)日：2018-07-17
申请号：US15291415
申请日：2016-10-12
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Chan Sic Yoon , Ki Seok Lee , Dong Oh Kim
IPC分类号： H01L21/027 , H01L21/033 , H01L21/308 , H01L21/3213 , H01L21/8234
摘要： A method for manufacturing a semiconductor device includes forming features of a first mold pattern on a substrate including a first region and a second region, and forming a first insulation layer covering the first mold pattern from the first region to the second region. The method further includes forming a photoresist pattern on the first insulation layer in the second region, forming a second insulation layer covering the first insulation layer in the first region and the photoresist pattern in the second region from the first region to the second region, etching the second insulation layer, removing the photoresist pattern, and forming a first double patterning technology pattern having a first width in the first region and a second DPT pattern having a second width in the second region, wherein the second width is different from the first width.

3. 发明申请

US20200295013A1 SEMICONDUCTOR DEVICE COMPRISING WORK FUNCTION METAL PATTERN IN BOUNDRY REGION AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20200295013A1
公开(公告)日：2020-09-17
申请号：US16890456
申请日：2020-06-02
申请人： Samsung Electronics Co., Ltd.
发明人： Ki Wook Jung , Dong Oh Kim , Seok Han Park , Chan Sic Yoon , Ki Seok Lee , Ho In Lee , Ju Yeon Jang , Je Min Park , Jin Woo Hong
IPC分类号： H01L27/11 , H01L27/092 , H01L27/108 , H01L29/10 , H01L21/8238 , H01L23/535
摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

4. 发明授权

US09916979B2 Methods for manufacturing a semiconductor device 有权
公开(公告)号：US09916979B2
公开(公告)日：2018-03-13
申请号：US15381135
申请日：2016-12-16
申请人： Samsung Electronics Co., Ltd.
发明人： Chan Sic Yoon , Ki Seok Lee , Dong Oh Kim , Yong Jae Kim
IPC分类号： H01L21/02 , H01L21/027 , G03F1/38
CPC分类号： H01L21/027 , G03F1/38 , H01L21/02107 , H01L21/02697 , H01L27/0207 , H01L27/10888
摘要： Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

5. 发明授权

US10679997B2 Semiconductor device comprising work function metal pattern in boundary region and method for fabricating the same 有权
公开(公告)号：US10679997B2
公开(公告)日：2020-06-09
申请号：US16391888
申请日：2019-04-23
申请人： Samsung Electronics Co., Ltd.
发明人： Ki Wook Jung , Dong Oh Kim , Seok Han Park , Chan Sic Yoon , Ki Seok Lee , Ho In Lee , Ju Yeon Jang , Je Min Park , Jin Woo Hong
IPC分类号： H01L27/108 , H01L21/8238 , H01L27/11 , H01L27/092 , H01L29/10 , H01L23/535
摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

6. 发明授权

US10325802B2 Method for fabricating semiconductor device 有权
公开(公告)号：US10325802B2
公开(公告)日：2019-06-18
申请号：US15712410
申请日：2017-09-22
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ho In Lee , Dong Oh Kim , Seok Han Park , Chan Sic Yoon , Ki Wook Jung , Jinwoo Augustin Hong , Je Min Park , Ki Seok Lee , Ju Yeon Jang
IPC分类号： H01L21/762 , H01L27/108 , H01L21/768 , H01L21/8234 , H01L29/66 , H01L29/786 , H01L27/12 , H01L29/43 , H01L29/06
摘要： A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.

7. 发明申请

US20220173112A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20220173112A1
公开(公告)日：2022-06-02
申请号：US17406418
申请日：2021-08-19
申请人： Samsung Electronics Co., Ltd.
发明人： Dong Oh Kim , Gyu Hyun Kil , Jung Hoon Han , Doo San Back
IPC分类号： H01L27/108
摘要： A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.

8. 发明授权

US10998324B2 Semiconductor device comprising work function metal pattern in boundary region and method for fabricating the same 有权
公开(公告)号：US10998324B2
公开(公告)日：2021-05-04
申请号：US16890456
申请日：2020-06-02
申请人： Samsung Electronics Co., Ltd.
发明人： Ki Wook Jung , Dong Oh Kim , Seok Han Park , Chan Sic Yoon , Ki Seok Lee , Ho In Lee , Ju Yeon Jang , Je Min Park , Jin Woo Hong
IPC分类号： H01L27/11 , H01L27/092 , H01L27/108 , H01L29/10 , H01L21/8238 , H01L23/535
摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

9. 发明授权

US10332894B2 Semiconductor device comprising work function metal pattern in boundry region and method for fabricating the same 有权
公开(公告)号：US10332894B2
公开(公告)日：2019-06-25
申请号：US15828934
申请日：2017-12-01
申请人： Samsung Electronics Co., Ltd.
发明人： Ki Wook Jung , Dong Oh Kim , Seok Han Park , Chan Sic Yoon , Ki Seok Lee , Ho In Lee , Ju Yeon Jang , Je Min Park , Jin Woo Hong
IPC分类号： H01L27/11 , H01L29/10 , H01L27/108 , H01L21/8238 , H01L27/092
摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

10. 发明申请

US20180158669A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180158669A1
公开(公告)日：2018-06-07
申请号：US15886372
申请日：2018-02-01
申请人： Samsung Electronics Co., Ltd.
发明人： Chan Sic Yoon , Ki Seok Lee , Dong Oh Kim , Yong Jae Kim
IPC分类号： H01L21/027 , H01L21/02 , G03F1/38
CPC分类号： H01L21/027 , G03F1/38 , H01L21/02107 , H01L21/02697 , H01L27/0207 , H01L27/10888
摘要： Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, fowling a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

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