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1. 发明授权

US08951881B2 Methods of fabricating nonvolatile memory devices including voids between active regions and related devices 有权
标题翻译：制造包括有源区域和相关器件之间的空隙的非易失性存储器件的方法
公开(公告)号：US08951881B2
公开(公告)日：2015-02-10
申请号：US14279786
申请日：2014-05-16
申请人： Samsung Electronics Co., Ltd.
发明人： Dong-Sik Lee , Jang-Hyun You , Jee-Hoon Han , Young-Woo Park , Sung-Hoi Hur , Sang-Ick Joo
IPC分类号： H01L21/76 , H01L21/762 , H01L21/764
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/764
摘要： A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.
摘要翻译：制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。沟槽和其间的有源区延伸到衬底的第一和第二器件区域。牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区在第二设备区域中。还讨论了相关的方法和设备。

2. 发明授权

US11626417B2 Three-dimensional semiconductor memory device and method of fabricating the same 有权
公开(公告)号：US11626417B2
公开(公告)日：2023-04-11
申请号：US17113456
申请日：2020-12-07
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dong-Sik Lee , Byungjin Lee , Sung-Min Hwang
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11526 , H01L27/11573 , H01L27/11519 , H01L27/11565
摘要： A three-dimensional semiconductor memory device includes a substrate including cell and connection regions. An electrode structure is disposed on the substrate, the electrode structure having a staircase structure on the connection region. A first vertical channel structure and a first dummy structure at least partially penetrate the electrode structure on the cell region and the connection region, respectively. Bottoms of expanded portions of the first vertical channel structure and the first dummy structure are located at first and second levels, respectively. The second level is higher than the first level.

3. 发明授权

US11587947B2 Three-dimensional semiconductor memory devices 有权
公开(公告)号：US11587947B2
公开(公告)日：2023-02-21
申请号：US17355824
申请日：2021-06-23
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kang-Won Lee , Jaeyoung Song , Dong-Sik Lee , Donghoon Jang
IPC分类号： H01L27/11582 , H01L27/115 , H01L27/1157 , H01L27/1156 , H01L23/522 , H01L27/1158 , H01L23/528
摘要： In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

4. 发明申请

US20210320126A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权
公开(公告)号：US20210320126A1
公开(公告)日：2021-10-14
申请号：US17355824
申请日：2021-06-23
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kang-Won Lee , Jaeyoung Song , Dong-Sik Lee , Donghoon Jang
IPC分类号： H01L27/11582 , H01L23/522 , H01L27/1157
摘要： In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penetrates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

5. 发明授权

US10818678B2 Three-dimensional semiconductor memory device and method of fabricating the same 有权
公开(公告)号：US10818678B2
公开(公告)日：2020-10-27
申请号：US15954151
申请日：2018-04-16
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sung-Min Hwang , Dong-Sik Lee , Joon-Sung Lim
IPC分类号： H01L27/112 , H01L27/11556 , H01L27/11582 , H01L23/532 , H01L27/11573 , H01L29/06 , H01L27/11526 , H01L27/11575
摘要： A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.

6. 发明授权

US10700085B2 Vertical memory devices 有权
公开(公告)号：US10700085B2
公开(公告)日：2020-06-30
申请号：US16010743
申请日：2018-06-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sung-Min Hwang , Dong-Sik Lee , Joon-Sung Lim
IPC分类号： H01L27/11582 , H01L27/11568 , H01L27/11573 , H01L23/528 , H01L23/522 , H01L27/11565 , H01L27/11575 , H01L27/1157 , H01L21/768 , H01L21/265 , H01L21/311 , H01L21/027 , H01L21/3105 , H01L21/02 , H01L21/28
摘要： A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.

7. 发明授权

US09711531B2 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US09711531B2
公开(公告)日：2017-07-18
申请号：US15285682
申请日：2016-10-05
申请人： Samsung Electronics Co., Ltd.
发明人： Woong-Seop Lee , Jongyoon Choi , Jinhyun Shin , Dong-Sik Lee
IPC分类号： H01L29/76 , H01L27/11582 , H01L29/10 , H01L27/11568 , H01L29/04 , H01L27/11565 , H01L29/423 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/0243 , H01L21/02636 , H01L27/11565 , H01L27/11568 , H01L29/04 , H01L29/1037 , H01L29/1054 , H01L29/4234 , H01L29/7827
摘要： A method of fabricating a semiconductor device can include forming a channel hole in a vertical stack of alternating insulating and sacrificial layers to form a recess in a substrate. A selectively epitaxial growth can be performed to provide a lower semiconductor pattern in the recess using material of the substrate as a seed and a recess can be formed to penetrate an upper surface of the lower semiconductor pattern via the channel hole.

8. 发明授权

US10903236B2 Three-dimensional semiconductor memory device 有权
公开(公告)号：US10903236B2
公开(公告)日：2021-01-26
申请号：US16663228
申请日：2019-10-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kangyoon Choi , Dong-Sik Lee , Jongwon Kim , Gilsung Lee , Eunsuk Cho , Byungyong Choi , Sung-Min Hwang
IPC分类号： H01L27/11582 , H01L23/522 , H01L27/11565 , H01L27/11573 , H01L29/04 , H01L23/528 , H01L21/768 , H01L21/311 , H01L21/3105 , H01L21/28 , H01L21/02
摘要： A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.

9. 发明授权

US09659958B2 Three-dimensional semiconductor memory device 有权
公开(公告)号：US09659958B2
公开(公告)日：2017-05-23
申请号：US15291521
申请日：2016-10-12
申请人： Samsung Electronics Co., Ltd.
发明人： Jung Hoon Lee , Keejeong Rho , Sejun Park , Jinhyun Shin , Dong-Sik Lee , Woong-Seop Lee
IPC分类号： H01L27/115 , H01L23/528 , H01L27/11582 , H01L27/11556
CPC分类号： H01L27/11582 , G11C16/08 , H01L23/528 , H01L27/11556 , H01L27/1157
摘要： A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

10. 发明授权

US09601577B1 Three-dimensionally integrated circuit devices including oxidation suppression layers 有权
公开(公告)号：US09601577B1
公开(公告)日：2017-03-21
申请号：US15251510
申请日：2016-08-30
申请人： Samsung Electronics Co., Ltd.
发明人： Dong-Sik Lee , Youngwoo Kim , Jinhyun Shin , Jung Hoon Lee
IPC分类号： H01L29/10 , H01L27/115 , H01L23/522 , H01L23/528 , H01L29/423 , G11C16/08
CPC分类号： H01L27/11551 , H01L21/26506 , H01L21/28158 , H01L21/823462 , H01L27/10897 , H01L27/1104 , H01L27/1116 , H01L27/11246 , H01L27/115 , H01L27/11529 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L27/11597 , H01L28/00 , H01L29/1083 , H01L29/42368
摘要： A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.

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