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1. 发明授权

US11355434B2 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US11355434B2
公开(公告)日：2022-06-07
申请号：US17016977
申请日：2020-09-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hyun-Seung Song , Kwang-Young Lee , Jonghyun Lee
IPC分类号： H01L23/528 , H01L27/11 , H01L21/768 , H01L29/78
摘要： A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.

2. 发明授权

US09799607B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US09799607B2
公开(公告)日：2017-10-24
申请号：US15358217
申请日：2016-11-22
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Seung Song , Hyeonuk Kim
IPC分类号： H01L21/82 , H01L27/02 , H01L23/535 , H01L27/088 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L29/417
CPC分类号： H01L23/535 , H01L21/823475 , H01L21/823871 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/41725 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction. The second sub-contact is connected to the first sub-contacts and is in contact with a top surface of the first gate electrode. In the first direction, each of the first sub-contacts has a first width and the second sub-contact has a second width smaller than the first width.

3. 发明授权

US09406663B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US09406663B2
公开(公告)日：2016-08-02
申请号：US14161867
申请日：2014-01-23
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Seung Song , Kyung-Eun Kim , Jae-Kyun Park
IPC分类号： H01L27/02 , H01L27/11 , H01L27/118
CPC分类号： H01L27/0207 , H01L27/1104 , H01L2027/11812 , H01L2027/11838
摘要： Semiconductor devices include a first gate pattern provided on the first active region, a second gate pattern over the first active region, a third gate pattern over the second active region, and a fourth gate pattern over the second active region. The second gate pattern is parallel to the first gate pattern in a first direction. The third gate pattern has an asymmetric shape to the first gate pattern with respect to the first direction, and the fourth gate pattern is parallel to the third gate pattern in the first direction, and has an asymmetric shape to the second gate pattern with respect to the first direction. MOS transistors having good properties may be provided in a narrow horizontal area. The MOS transistors may be used in highly stacked semiconductor devices.
摘要翻译：半导体器件包括设置在第一有源区上的第一栅极图案，第一有源区上的第二栅极图案，第二有源区上的第三栅极图案，以及第二有源区上的第四栅极图案。第二栅极图案在第一方向上平行于第一栅极图案。第三栅极图案相对于第一方向具有与第一栅极图案不对称的形状，并且第四栅极图案在第一方向上平行于第三栅极图案，并且相对于第二栅极图案具有与第二栅极图案不对称的形状第一个方向。可以在窄的水平区域中提供具有良好性能的MOS晶体管。 MOS晶体管可以用于高度堆叠的半导体器件中。

4. 发明授权

US11923298B2 Method of fabricating semiconductor device 有权
公开(公告)号：US11923298B2
公开(公告)日：2024-03-05
申请号：US17830811
申请日：2022-06-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hyun-Seung Song , Kwang-Young Lee , Jonghyun Lee
IPC分类号： H01L23/528 , H01L21/768 , H10B10/00 , H01L29/78
CPC分类号： H01L23/528 , H01L21/76802 , H01L21/76834 , H10B10/12 , H01L21/76843 , H01L29/785
摘要： A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.

5. 发明申请

US20220199798A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20220199798A1
公开(公告)日：2022-06-23
申请号：US17457661
申请日：2021-12-05
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Myung Gil Kang , Keun Hwi Cho , Sangdeok Kwon , Dongwon Kim , Hyun-Seung Song
IPC分类号： H01L29/423 , H01L23/522 , H01L27/088 , H01L29/786
摘要： A semiconductor device includes a substrate that includes a peripheral region, a first active pattern on the peripheral region, a first source/drain pattern on the first active pattern, a first channel pattern formed on the first active pattern and connected to the first source/drain pattern, wherein the first channel pattern includes semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode that extends in a first direction and crosses the first channel pattern, a gate insulating layer interposed between the first gate electrode and the first channel pattern, a first gate contact disposed on the first gate electrode and that extends in the first direction, and a first dielectric layer interposed between the first gate electrode and the first gate contact. The first dielectric layer is interposed between the first gate contact and the first gate electrode and extends in the first direction.

6. 发明授权

US09548390B2 Semiconductor device including field effect transistor 有权
标题翻译：包括场效应晶体管的半导体器件
公开(公告)号：US09548390B2
公开(公告)日：2017-01-17
申请号：US14742710
申请日：2015-06-18
申请人： Samsung Electronics Co., Ltd.
发明人： Jongun Kim , Dong-Hyun Kim , Hyun-Seung Song
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66 , H01L27/088 , H01L29/06 , H01L29/10 , H01L29/165
CPC分类号： H01L29/7851 , H01L27/0886 , H01L29/0649 , H01L29/1037 , H01L29/165 , H01L29/42392 , H01L29/66545 , H01L29/66818 , H01L29/7848 , H01L29/7853 , H01L2029/7858
摘要： A semiconductor device includes a fin portion protruding from a substrate. The fin portion includes a base part, an intermediate part on the base part, and a channel part on the intermediate part. A width of the intermediate part is less than a width of the base part and greater than a width of the channel part. A gate electrode coves both sidewalls and a top surface of the channel part, and a device isolation pattern covers both sidewalls of the base part and both sidewalls of the intermediate part.
摘要翻译：半导体器件包括从衬底突出的鳍部。翅片部分包括基部，基部上的中间部分和中间部分上的通道部分。中间部分的宽度小于基部的宽度并且大于通道部分的宽度。栅极电极使沟道部分的两个侧壁和顶表面均匀，并且器件隔离图案覆盖基部的两个侧壁和中间部分的两个侧壁。

7. 发明申请

US20160307887A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING A RESISTOR STRUCTURE 审中-公开
标题翻译：制造具有电阻结构的半导体器件的方法
公开(公告)号：US20160307887A1
公开(公告)日：2016-10-20
申请号：US15196781
申请日：2016-06-29
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Seung Song , Hwi-Chan Jun
IPC分类号： H01L27/06 , H01L29/66 , H01L21/8234 , H01L23/532 , H01L21/768 , H01L21/285 , H01L49/02 , H01L23/535
CPC分类号： H01L27/0629 , H01L21/28518 , H01L21/28568 , H01L21/76805 , H01L21/76816 , H01L21/76843 , H01L21/76855 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L23/485 , H01L23/5228 , H01L23/53266 , H01L23/535 , H01L28/24 , H01L29/456 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.
摘要翻译：提供一种制造半导体器件的方法。该方法包括提供包括晶体管区域和电阻器区域的衬底，在电阻器区域中的衬底上形成伪栅极结构和下层间绝缘层; 形成具有缓冲绝缘图案的电阻器结构，电阻元件和顺序地设置在下层间绝缘层上的蚀刻延迟图案; 以及形成电阻器接触结构，其被配置为穿过所述蚀刻延迟图案并与所述电阻器元件接触。

8. 发明申请

US20150044829A1 Methods of Fabricating Semiconductor Devices Having Punch-Through Stopping Regions 有权
标题翻译：制造具有穿通停止区域的半导体器件的方法
公开(公告)号：US20150044829A1
公开(公告)日：2015-02-12
申请号：US14454943
申请日：2014-08-08
申请人： Samsung Electronics Co., Ltd.
发明人： Jong-Un Kim , Hyun-Seung Song , Dong-Hyun Kim
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/266
CPC分类号： H01L29/7851 , H01L21/266 , H01L21/823807 , H01L21/823821 , H01L27/0921 , H01L27/0924 , H01L29/66803
摘要： Methods of fabricating semiconductor devices are provided including providing a substrate having a first region and a second region, the substrate defining trenches in the first and second regions; forming active fins on the first and second regions, the active fins protruding from the trenches in the first and second regions; forming spacers on sidewalls of the active fins in the first and second regions; recessing floors of the trenches under the spacers to provide extensions of the active fins; implanting impurities of a first type in the extensions of the active fins in the first region; and implanting impurities of a second, type, different from the first type, in the extensions of the active fins in the second region.
摘要翻译：提供制造半导体器件的方法包括提供具有第一区域和第二区域的衬底，所述衬底限定第一和第二区域中的沟槽; 在所述第一和第二区域上形成活动翅片，所述活动翅片从所述第一和第二区域中的沟槽突出; 在所述第一和第二区域中的活动翅片的侧壁上形成间隔物; 在间隔物下方的沟槽的凹陷地板，以提供活动鳍片的延伸; 将第一类型的杂质植入第一区域中活性鳍片的延伸部分; 以及将第二类型的不同于第一类型的杂质植入第二区域中的活性鳍片的延伸部分。

9. 发明申请

US20230011401A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
公开(公告)号：US20230011401A1
公开(公告)日：2023-01-12
申请号：US17932851
申请日：2022-09-16
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Seung Song , Tae-Yeol Kim , Jae-Jik Baek
IPC分类号： H01L29/417 , H01L23/522 , H01L29/40
摘要： A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

10. 发明授权

US11482602B2 Semiconductor devices and methods of fabricating the same 有权
公开(公告)号：US11482602B2
公开(公告)日：2022-10-25
申请号：US17034088
申请日：2020-09-28
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Seung Song , Tae-Yeol Kim , Jae-Jik Baek
IPC分类号： H01L29/417 , H01L23/522 , H01L29/40
摘要： A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

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