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1. 发明授权

US10892347B2 Vertical tunneling field effect transistor and method for manufacturing the same 有权
公开(公告)号：US10892347B2
公开(公告)日：2021-01-12
申请号：US16197752
申请日：2018-11-21
申请人： Samsung Electronics Co., Ltd.
发明人： Kyung Yub Jeon , Tae Yong Kwon , Oh Seong Kwon , Soo Yeon Jeong , Yong Hee Park , Jong Ryeol Yoo
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L29/423 , H01L29/786 , H01L29/739
摘要： A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

2. 发明授权

US10804391B2 Vertical field-effect transistor (VFET) devices and methods of forming the same 有权
公开(公告)号：US10804391B2
公开(公告)日：2020-10-13
申请号：US16286023
申请日：2019-02-26
申请人： Samsung Electronics Co., Ltd. , International Business Machines Corporation
发明人： Tae Yong Kwon , Kang Ill Seo , Oh Seong Kwon , Ki Sik Choi
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/66
摘要： Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.

3. 发明授权

US10566245B2 Method of fabricating gate all around semiconductor device 有权
公开(公告)号：US10566245B2
公开(公告)日：2020-02-18
申请号：US15854343
申请日：2017-12-26
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Tae Yong Kwon , Oh Seong Kwon
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/49 , H01L21/027 , H01L21/311 , H01L29/423
摘要： A method of fabricating a gate all around semiconductor device is provided. The method includes: providing a semiconductor substrate having a plurality of active fins extending in a first direction in a first region and a second region next to the first region, a plurality of gate all around channels stacked above each of the plurality of active fins, and a plurality of gate openings extending in a second direction across the first and second regions and crossing the plurality of active fins, in which the plurality of gate openings include cave-like gate spaces between each of the plurality of active fins and one adjacent gate all around channel and between two adjacent gate all around channels, forming a dielectric layer in the first and second regions on bottom and sidewalls of each of the plurality of gate openings, and on and surrounding each of the plurality of gate all around channels and filling a first portion of each of the cave-like gate spaces, forming first work function metal in the first and second regions on the dielectric layer with the first work function metal filling a second portion of each of the cave-like gate spaces, forming first carbon-based mask in the first and second regions by a chemical vapor deposition (CVD) process to fill the plurality of gate openings to a height at least covering all the plurality of gate all around channels, forming second carbon-based mask in the first and second regions on top of the first carbon-based mask to a height above the plurality of gate openings, removing the first and second carbon-based masks in the second region, removing the first work function metal in the second region through etching using remaining first and second carbon-based masks in the first region as an etching mask, removing the remaining first and second carbon-based masks in the first region, and forming second work function metal on the dielectric layer in the second region, and on the first work function metal in the first region.

4. 发明申请

US20190386136A1 VERTICAL FIELD-EFFECT TRANSISTOR (VFET) DEVICES AND METHODS OF FORMING THE SAME 审中-公开
公开(公告)号：US20190386136A1
公开(公告)日：2019-12-19
申请号：US16286023
申请日：2019-02-26
申请人： Samsung Electronics Co., Ltd. , International Business Machines Corporation
发明人： Tae Yong KWON , Kang Ill Seo , Oh Seong Kwon , Ki Sik Choi
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8234
摘要： Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.

5. 发明授权

US10164057B1 Vertical tunneling field effect transistor and method for manufacturing the same 有权
公开(公告)号：US10164057B1
公开(公告)日：2018-12-25
申请号：US15878711
申请日：2018-01-24
申请人： Samsung Electronics Co., Ltd.
发明人： Kyung Yub Jeon , Tae Yong Kwon , Oh Seong Kwon , Soo Yeon Jeong , Yong Hee Park , Jong Ryeol Yoo
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L29/423
摘要： A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

6. 发明申请

US20180315667A1 METHOD OF FABRICATING GATE ALL AROUND SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180315667A1
公开(公告)日：2018-11-01
申请号：US15854343
申请日：2017-12-26
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Tae Yong Kwon , Oh Seong Kwon
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/423 , H01L21/027 , H01L21/311 , H01L29/49
摘要： A method of fabricating a gate all around semiconductor device is provided. The method includes: providing a semiconductor substrate having a plurality of active fins extending in a first direction in a first region and a second region next to the first region, a plurality of gate all around channels stacked above each of the plurality of active fins, and a plurality of gate openings extending in a second direction across the first and second regions and crossing the plurality of active fins, in which the plurality of gate openings include cave-like gate spaces between each of the plurality of active fins and one adjacent gate all around channel and between two adjacent gate all around channels, forming a dielectric layer in the first and second regions on bottom and sidewalls of each of the plurality of gate openings, and on and surrounding each of the plurality of gate all around channels and filling a first portion of each of the cave-like gate spaces, forming first work function metal in the first and second regions on the dielectric layer with the first work function metal filling a second portion of each of the cave-like gate spaces, forming first carbon-based mask in the first and second regions by a chemical vapor deposition (CVD) process to fill the plurality of gate openings to a height at least covering all the plurality of gate all around channels, forming second carbon-based mask in the first and second regions on top of the first carbon-based mask to a height above the plurality of gate openings, removing the first and second carbon-based masks in the second region, removing the first work function metal in the second region through etching using remaining first and second carbon-based masks in the first region as an etching mask, removing the remaining first and second carbon-based masks in the first region, and forming second work function metal on the dielectric layer in the second region, and on the first work function metal in the first region.

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