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1. 发明授权

US11626421B2 Vertical memory device and method of fabrication the same 有权
公开(公告)号：US11626421B2
公开(公告)日：2023-04-11
申请号：US17196005
申请日：2021-03-09
申请人： Samsung Electronics Co., Ltd.
发明人： Seok Cheon Baek
IPC分类号： H01L27/11582 , H01L21/02 , H01L21/768 , H01L29/10 , H01L23/48 , H01L23/528 , H01L27/11565 , H01L27/11568 , H01L27/11573
摘要： A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

2. 发明授权

US11056502B2 Semiconductor device including multi-stack structure 有权
公开(公告)号：US11056502B2
公开(公告)日：2021-07-06
申请号：US16365827
申请日：2019-03-27
申请人： Samsung Electronics Co., Ltd.
发明人： Seok Cheon Baek
IPC分类号： H01L23/538 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/11573 , H01L29/66 , H01L27/11568 , H01L27/11575
摘要： A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.

3. 发明授权

US10971432B2 Semiconductor device including a through wiring area 有权
公开(公告)号：US10971432B2
公开(公告)日：2021-04-06
申请号：US16388370
申请日：2019-04-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Seok Cheon Baek
IPC分类号： H01L23/48 , H01L27/11582 , H01L27/11556
摘要： A semiconductor device includes a peripheral circuit area disposed on a first substrate and including circuit devices. A memory cell area is disposed on a second substrate and includes memory cells. A through wiring area includes a through contact plug and an insulating area. The through contact plug extends through the memory cell area and the second substrate and connects the memory cell area to the circuit devices. The insulating area surrounds the through contact plug. The insulating area includes a first insulating layer penetrating through the second substrate, a plurality of second insulating layers, a third insulating layer having a vertical extension portion, and a plurality of horizontal extension portions extended in parallel to a top surface of the second substrate from a side surface of the vertical extension portion to contact the second insulating layers.

4. 发明授权

US11476265B2 Three-dimensional semiconductor device 有权
公开(公告)号：US11476265B2
公开(公告)日：2022-10-18
申请号：US16401205
申请日：2019-05-02
申请人： Samsung Electronics Co., Ltd.
发明人： Seok Cheon Baek
IPC分类号： H01L27/11556 , H01L27/02 , G11C5/06 , H01L27/11582
摘要： A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion. The intermediate interlayer insulation layer has the same thickness as that of an interlayer insulation layer adjacent in the vertical direction.

5. 发明申请

US20200185402A1 SEMICONDUCTOR DEVICES INCLUDING CHANNEL STRUCTURES 审中-公开
公开(公告)号：US20200185402A1
公开(公告)日：2020-06-11
申请号：US16454293
申请日：2019-06-27
申请人： Samsung Electronics Co., Ltd.
发明人： YOON HWAN SON , Seok Cheon Baek , Ji Sung Cheon
IPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11568
摘要： A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.

6. 发明申请

US20190333872A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20190333872A1
公开(公告)日：2019-10-31
申请号：US16227919
申请日：2018-12-20
申请人： Samsung Electronics Co., Ltd.
发明人： Geun Won Lim , Seok Cheon Baek , Ji Sung Cheon , Jong Woo Shin , Bong Hyun Choi
IPC分类号： H01L23/00 , H01L27/11582 , H01L27/11573
摘要： A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

7. 发明授权

US11145672B2 Semiconductor device including stack structures having gate pads with different thicknesses 有权
公开(公告)号：US11145672B2
公开(公告)日：2021-10-12
申请号：US16706684
申请日：2019-12-07
申请人： Samsung Electronics Co., Ltd.
发明人： Seok Cheon Baek , Boh Chang Kim , Chung Ki Min , Ji Hoon Park , Byung Kwan You
IPC分类号： H01L27/11582 , H01L23/00 , H01L29/423 , H01L27/11565 , H01L27/11548 , H01L27/11575 , H01L27/11556 , H01L27/1157 , H01L21/768 , H01L23/538 , H01L27/11531
摘要： A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

8. 发明授权

US10903229B2 Three-dimensional semiconductor memory device with central connection through region 有权
公开(公告)号：US10903229B2
公开(公告)日：2021-01-26
申请号：US16162533
申请日：2018-10-17
申请人： Samsung Electronics Co., Ltd.
发明人： Seok Cheon Baek , Sung Hun Lee
IPC分类号： H01L27/11582 , H01L27/11573 , H01L29/423 , G11C7/18 , G11C8/14 , H01L27/1157 , G11C5/02
摘要： A three-dimensional semiconductor memory device including a gate-stack structure on a base substrate, the gate-stack structure including gate electrodes stacked in a direction perpendicular to a surface of the base substrate and spaced apart from each other; a through region penetrating through the gate-stack structure and surrounded by the gate-stack structure; and first vertical channel structures and second vertical channel structures on both sides of the through region and penetrating through the gate-stack structure, wherein the through region is between the first vertical channel structures and the second vertical channel structures.

9. 发明授权

US10930664B2 Semiconductor devices including channel structures 有权
公开(公告)号：US10930664B2
公开(公告)日：2021-02-23
申请号：US16454293
申请日：2019-06-27
申请人： Samsung Electronics Co., Ltd.
发明人： Yoon Hwan Son , Seok Cheon Baek , Ji Sung Cheon
IPC分类号： H01L27/115 , H01L27/11578 , H01L27/11568 , H01L27/11565
摘要： A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.

10. 发明授权

US10535679B2 Semiconductor device including stack structures having R-type pad and P-type pad of different thickness 有权
公开(公告)号：US10535679B2
公开(公告)日：2020-01-14
申请号：US16136474
申请日：2018-09-20
申请人： Samsung Electronics Co., Ltd.
发明人： Seok Cheon Baek , Boh Chang Kim , Chung Ki Min , Ji Hoon Park , Byung Kwan You
IPC分类号： H01L27/11582 , H01L29/423 , H01L23/00
摘要： A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

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