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1. 发明授权

US09384861B2 Data loading circuit and semiconductor memory device comprising same 有权
公开(公告)号：US09384861B2
公开(公告)日：2016-07-05
申请号：US14623133
申请日：2015-02-16
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jong-Min Oh , Ho-Young Song , Seong-Jin Jang
IPC分类号： G11C19/00 , G11C11/4093 , G11C7/10 , G11C29/00 , G11C8/04 , G11C16/20 , G11C17/16 , G11C29/04
CPC分类号： G11C29/86 , G11C7/1036 , G11C7/1051 , G11C8/04 , G11C11/4093 , G11C16/20 , G11C17/16 , G11C2029/0407 , G11C2207/107
摘要： A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.

2. 发明授权

US10090066B2 Semiconductor memory devices, memory systems including the same and method of correcting errors in the same 有权
公开(公告)号：US10090066B2
公开(公告)日：2018-10-02
申请号：US15696794
申请日：2017-09-06
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Uhn Cha , Hoi-Ju Chung , Jong-Pil Son , Kwang-Il Park , Seong-Jin Jang
IPC分类号： G06F11/10 , G11C29/52 , G11C29/00 , G11C11/15 , G11C29/04 , G11C29/44
摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

3. 发明授权

US09711192B2 Memory device having different data-size access modes for different power modes 有权
公开(公告)号：US09711192B2
公开(公告)日：2017-07-18
申请号：US14931291
申请日：2015-11-03
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hye-Ran Kim , Tae-Young Oh , Seong-Jin Jang
IPC分类号： G11C5/14 , G11C7/10 , G11C8/12
CPC分类号： G11C5/147 , G11C5/148 , G11C7/1006 , G11C7/1045 , G11C7/1057 , G11C7/1084 , G11C8/12 , G11C2207/2227
摘要： A memory device that operates in a low-power operation mode includes a memory cell array, a page size changing circuit, and an encoding and decoding changing circuit. The page size changing circuit changes the number of data items prefetched in the memory cell array according to a power mode during a read operation. The encoding and decoding changing circuit changes a level of data written in the memory cell array according to the power mode during a read operation.

4. 发明授权

US09727412B2 Memory device having error notification function 有权
公开(公告)号：US09727412B2
公开(公告)日：2017-08-08
申请号：US14729656
申请日：2015-06-03
申请人： Samsung Electronics Co., Ltd.
发明人： Jong-Pil Son , Chul-Woo Park , Seong-Jin Jang , Hoi-Ju Chung , Sang-Uhn Cha
IPC分类号： G06F11/00 , G06F11/10 , G06F11/16 , G11C29/04
CPC分类号： G06F11/1008 , G06F11/1004 , G06F11/1024 , G06F11/1068 , G06F11/1666 , G11C2029/0411
摘要： A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

5. 发明授权

US10127102B2 Semiconductor memory devices and memory systems including the same 有权
公开(公告)号：US10127102B2
公开(公告)日：2018-11-13
申请号：US15229774
申请日：2016-08-05
申请人： Samsung Electronics Co., Ltd.
发明人： Ye-Sin Ryu , Hoi-Ju Chung , Sang-Uhn Cha , Young-Yong Byun , Seong-Jin Jang
IPC分类号： G11C29/00 , G06F11/10 , G11C29/52 , G06F3/06
摘要： A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.

6. 发明授权

US09805827B2 Semiconductor memory devices, memory systems including the same and methods of operating the same 有权
公开(公告)号：US09805827B2
公开(公告)日：2017-10-31
申请号：US14817212
申请日：2015-08-04
申请人： Samsung Electronics Co., Ltd.
发明人： Jong-Pil Son , Chul-Woo Park , Hoi-Ju Chung , Sang-Uhn Cha , Seong-Jin Jang
IPC分类号： G11C11/16 , G11C11/4096 , G11C29/42 , G11C29/44
CPC分类号： G11C29/4401 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4096 , G11C29/42 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

7. 发明授权

US09343175B2 Fuse data reading circuit having multiple reading modes and related devices, systems and methods 有权
标题翻译：具有多种读取模式和相关设备，系统和方法的保险丝数据读取电路
公开(公告)号：US09343175B2
公开(公告)日：2016-05-17
申请号：US13835319
申请日：2013-03-15
申请人： Samsung Electronics Co., Ltd.
发明人： Gil-Su Kim , Jong-Min Oh , Sung-Min Seo , Je-Min Ryu , Seong-Jin Jang
IPC分类号： G11C17/00 , G11C17/18 , G11C7/14 , G11C17/16 , G11C29/00
CPC分类号： G11C17/18 , G11C7/14 , G11C17/16 , G11C29/789
摘要： A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.
摘要翻译：熔丝数据读取电路被配置为以多读取模式读取熔丝数据。熔丝数据可以存储在包括被配置为存储熔丝数据的多个熔丝单元的熔丝阵列中。熔丝数据读取电路可以包括感测单元，其被配置为感测存储在熔丝阵列的熔丝单元中的熔丝数据，以及控制器，被配置为控制读取存储在熔丝单元中的熔丝数据的操作。控制器根据熔丝数据读取操作期间的操作周期设置感测熔丝数据的不同感测条件以读取熔丝数据。方法包括操作和使用熔丝数据读取电路。

8. 发明授权

US08988950B2 Data loading circuit and semiconductor memory device comprising same 有权
标题翻译：数据加载电路和包含该数据加载电路的半导体存储器件
公开(公告)号：US08988950B2
公开(公告)日：2015-03-24
申请号：US14056370
申请日：2013-10-17
申请人： Samsung Electronics Co., Ltd.
发明人： Jong-Min Oh , Ho-Yong Song , Seong-Jin Jang
IPC分类号： G11C19/00 , G11C11/4093 , G11C7/10 , G11C8/04 , G11C29/04
CPC分类号： G11C29/86 , G11C7/1036 , G11C7/1051 , G11C8/04 , G11C11/4093 , G11C16/20 , G11C17/16 , G11C2029/0407 , G11C2207/107
摘要： A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.
摘要翻译：数据加载电路包括被配置为存储非易失性数据并响应于上电操作基于所存储的非易失性数据输出串行数据信号的非易失性存储器，被配置为接收串行数据信号的解串器和基于所接收的串行数据信号以单位周期的间隔输出多个数据位;负载控制器，被配置为生成在所述单位周期的每个间隔逐个依次激活的多个加载选择信号;以及加载存储器单元被配置为响应于所述加载选择信号在所述单位周期的每个间隔顺序地存储所述数据位。

9. 发明授权

US09312963B2 Optical transmission converter, memory system comprising same, and related method of operation 有权
标题翻译：光传输转换器，包括其的存储器系统及相关操作方法
公开(公告)号：US09312963B2
公开(公告)日：2016-04-12
申请号：US14552601
申请日：2014-11-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jeong-Kyoum Kim , Seok-Hun Hyun , In-Dal Song , Seong-Jin Jang , Jung-Hwan Choi
IPC分类号： H04B10/50 , H04B10/80 , H04B10/67 , H04B10/572 , H04J14/00 , H04J14/02
CPC分类号： H04B10/572 , H04B10/506 , H04B10/671 , H04B10/801 , H04J14/0278
摘要： An optical transmission converter comprises a wavelength selector configured to output a reception wavelength selection signal and a transmission wavelength selection signal in response to a wavelength control signal, an opto-electrical converter configured to convert a selection optical signal into a reception electrical signal based on a reception optical signal from a host device and the reception wavelength selection signal, and an electro-optical converter configured to convert a transmission electrical signal into a transmission optical signal based on the transmission wavelength selection signal and the transmission electrical signal.
摘要翻译：一种光传输转换器，包括：波长选择器，被配置为响应于波长控制信号输出接收波长选择信号和传输波长选择信号;光电转换器，被配置为基于选择光信号将选择光信号转换为接收电信号接收光信号和接收波长选择信号，以及电光转换器，被配置为基于传输波长选择信号和传输电信号将传输电信号转换为传输光信号。

10. 发明授权

US09036441B2 Anti-fuse circuit in which anti-fuse cell data is monitored, and semiconductor device including the same 有权
标题翻译：防熔丝电池数据被监视的反熔丝电路，以及包括其的半导体器件
公开(公告)号：US09036441B2
公开(公告)日：2015-05-19
申请号：US13793457
申请日：2013-03-11
申请人： Samsung Electronics Co., Ltd.
发明人： Jong-Min Oh , Ho-Young Song , Seong-Jin Jang
IPC分类号： G11C17/00 , G11C17/18 , G11C17/16 , G11C29/00
CPC分类号： G11C17/16 , G11C29/76
摘要： An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal.
摘要翻译：公开了一种其中可以在反熔丝电路外面监视反熔丝程序数据的反熔丝电路和包括反熔丝电路的半导体器件。反熔丝电路包括反熔丝阵列，数据存储电路和第一选择电路。反熔丝阵列包括一个或多个抗熔丝块，其包括具有多个反熔丝单元的第一反熔丝块，并且反熔丝阵列被配置为存储反熔丝程序数据。数据存储电路被配置为通过一个或多个数据总线接收并存储来自反熔丝阵列的反熔丝程序数据。第一选择电路被配置为响应于第一选择信号输出所述一个或多个反熔丝块的所选反熔丝块的反熔丝程序数据。

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