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1. 发明申请

US20200312877A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20200312877A1
公开(公告)日：2020-10-01
申请号：US16901171
申请日：2020-06-15
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Min HWANG , Joon-Sung LIM , Jihye KIM
IPC分类号： H01L27/11582 , H01L27/11575 , H01L27/11573 , H01L23/538 , H01L27/11556
摘要： A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.

2. 发明申请

US20190393243A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES INCLUDING VERTICAL STRUCTURES WITH VARIED SPACING 审中-公开
公开(公告)号：US20190393243A1
公开(公告)日：2019-12-26
申请号：US16563014
申请日：2019-09-06
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sungjoong KIM , Joon-Sung LIM , Sung-Min HWANG
IPC分类号： H01L27/11582 , H01L27/1157 , G11C16/04 , H01L29/423 , H01L29/66
摘要： A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.

3. 发明申请

US20180374867A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：US20180374867A1
公开(公告)日：2018-12-27
申请号：US15860082
申请日：2018-01-02
申请人： Samsung Electronics Co., Ltd.
发明人： Jang-Gn YUN , Sung-Min HWANG , Joon-Sung LIM , Kyoil KOO , Hoosung CHO , Sunyoung KIM , Cheol RYOU , Jaesun YUN
IPC分类号： H01L27/11582 , H01L29/10 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/1037 , H01L29/4234
摘要： Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.

4. 发明申请

US20220139855A1 SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权
公开(公告)号：US20220139855A1
公开(公告)日：2022-05-05
申请号：US17328176
申请日：2021-05-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sung-Min HWANG , Jiwon KIM , Jaeho AHN , Joon-Sung LIM , Sukkang SUNG
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573 , G11C16/08 , G11C16/10
摘要： A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

5. 发明申请

US20220130782A1 SEMICONDUCTOR MEMORY DEVICE, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD FOR FABRICATING THE SAME 有权
公开(公告)号：US20220130782A1
公开(公告)日：2022-04-28
申请号：US17389841
申请日：2021-07-30
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jae Ho AHN , Ji Won KIM , Sung-Min HWANG , Joon-Sung LIM , Suk Kang SUNG
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L23/535 , H01L21/768 , H01L25/00
摘要： A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

6. 发明申请

US20210111187A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
公开(公告)号：US20210111187A1
公开(公告)日：2021-04-15
申请号：US16890115
申请日：2020-06-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jae Ho AHN , Sung-Min HWANG , Joon-Sung LIM , Bum Kyu KANG , Sang Don LEE
IPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/11519 , H01L27/1157 , H01L27/11565
摘要： A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

7. 发明申请

US20200312862A1 SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20200312862A1
公开(公告)日：2020-10-01
申请号：US16902575
申请日：2020-06-16
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Min HWANG , Joon-Sung LIM , Eunsuk CHO
IPC分类号： H01L27/11573 , H01L27/1157 , H01L29/423 , H01L29/66 , H01L27/11582 , H01L25/065 , H01L27/11575
摘要： A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

8. 发明申请

US20180358376A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20180358376A1
公开(公告)日：2018-12-13
申请号：US15982213
申请日：2018-05-17
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Min HWANG , Joon-Sung LIM , Jihye KIM
IPC分类号： H01L27/11582 , H01L23/538 , H01L27/11556
摘要： A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.

9. 发明申请

US20150311213A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20150311213A1
公开(公告)日：2015-10-29
申请号：US14790724
申请日：2015-07-02
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Min HWANG , Han-Soo KIM , Woon-Kyung LEE , Won-Seok CHO
IPC分类号： H01L27/115
CPC分类号： H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.
摘要翻译：制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘部分堆叠结构以形成初步的阶梯状图案结构。初步阶形形状图案结构具有阶梯形边缘部分。形成与基板表面接触的柱结构。部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。第二开口部分切割下牺牲层的至少边缘部分。

10. 发明申请

US20230005942A1 THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权
公开(公告)号：US20230005942A1
公开(公告)日：2023-01-05
申请号：US17678473
申请日：2022-02-23
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Min HWANG , Jae-Joo SHIM , Dong-Sik LEE , Bongtae PARK
IPC分类号： H01L27/11539 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L23/522 , H01L23/528
摘要： A 3D semiconductor memory device includes a substrate, a stack structure comprising interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, vertical channel structures penetrating the stack structure, a separation structure spaced apart from the vertical channel structures and filling a trench crossing the stack structure, the separation structure comprising a spacer covering an inner sidewall of the trench, and a first conductive contact filling an inner space of the trench surrounded by the spacer, an insulating layer covering the substrate and the stack structure, contact plugs penetrating the insulating layer so as to be connected to the gate electrodes of the stack structure, and a second conductive contact spaced apart from the stack structure and penetrating the insulating layer so as to be connected to a peripheral circuit transistor. A bottom surface of the first conductive contact is at a level lower than a bottom surface of the spacer.

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