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1. 发明授权

US11126300B2 Electronic device and input processing method thereof 有权
公开(公告)号：US11126300B2
公开(公告)日：2021-09-21
申请号：US15598576
申请日：2017-05-18
申请人： Samsung Electronics Co., Ltd.
发明人： Kiseok Lee , Kyungwhoon Cheun , Dohy Hong , Sungkee Kim , Sungil Park , Changmin Ha
IPC分类号： G06F3/041 , G06F3/0484 , G06F3/0488
摘要： A method of processing an input in an electronic device having a touch screen is provided. The method includes identifying attribute information of a geometric figure corresponding to an area of a touch input detected through the touch screen, determining a user input from the attribute information, based on a stored user input distinction rule, and executing a function corresponding to the determined user input.

2. 发明申请

US20230139447A1 SEMICONDUCTOR DEVICES HAVING ASYMMETRICAL STRUCTURES 有权
公开(公告)号：US20230139447A1
公开(公告)日：2023-05-04
申请号：US18148233
申请日：2022-12-29
申请人： Samsung Electronics Co., Ltd.
发明人： Junggun YOU , Sungil Park , Joohee Jung , Sunggi Hur
IPC分类号： H01L27/088 , H01L21/8234
摘要： A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.

3. 发明授权

US09123774B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09123774B2
公开(公告)日：2015-09-01
申请号：US14162481
申请日：2014-01-23
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Dae Suk , Heesoo Kang , Sungil Park , Changwoo Oh
IPC分类号： H01L29/66 , H01L29/40 , H01L21/3205 , H01L21/764 , H01L29/78
CPC分类号： H01L21/764 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.
摘要翻译：提供了一种半导体器件，其包括跨越设置在衬底上的半导体翅片上的栅极电极，设置在栅极电极和半导体鳍片之间的栅极电介质层，具有限定在半导体鳍片下方的三维结构的沟道区域栅极电极，设置在栅电极两侧并与栅电极间隔开的半导体鳍片中的杂质区域，除了栅电极之外覆盖基板整个表面的第一层间电介质层，穿过第第一层间电介质层和与杂质区接触的第二层间电介质层和覆盖栅电极并部分地填充栅电极和杂质区之间的空间的第二层间电介质层，以限定栅电极和杂质区之间的气隙。

4. 发明申请

US20230046546A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20230046546A1
公开(公告)日：2023-02-16
申请号：US17699724
申请日：2022-03-21
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sungil Park , Jae Hyun Park , Doyoung Choi , Youngmoon Choi , Daewon Ha
IPC分类号： H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/8238 , H01L29/66
摘要： A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

5. 发明授权

US10256324B2 Semiconductor devices having vertical transistors with aligned gate electrodes 有权
公开(公告)号：US10256324B2
公开(公告)日：2019-04-09
申请号：US15664226
申请日：2017-07-31
申请人： Samsung Electronics Co., Ltd.
发明人： Sungil Park , Changhee Kim , Yunil Lee , Mirco Cantoro , Junggun You , Donghun Lee
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10 , H01L21/28 , H01L29/40 , H01L29/423
摘要： A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

6. 发明申请

US20170033107A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20170033107A1
公开(公告)日：2017-02-02
申请号：US15159978
申请日：2016-05-20
申请人： Samsung Electronics Co., Ltd.
发明人： Byoung Hak HONG , Sungil Park , Toshinori Fukai , Shigenobu Maeda , Sada-aki Masuoka , Sanghyun Lee , Keon Yong Cheon , Hock-Chun Chin
IPC分类号： H01L27/092 , H01L21/265 , H01L21/8234 , H01L21/02 , H01L29/06 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/02532 , H01L21/02636 , H01L21/26513 , H01L21/823412 , H01L21/823437 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L27/092 , H01L29/0649 , H01L29/78 , H01L29/7846 , H01L29/7848
摘要： A semiconductor device includes a substrate including at least one metal-oxide-semiconductor field-effect transistor (MOSFET) region defined by a device isolation layer and having an active pattern extending in a first direction on the MOSFET region, a gate electrode intersecting the active pattern on the substrate and extending in a second direction intersecting the first direction, and a first gate separation pattern adjacent to the MOSFET region when viewed from a plan view and dividing the gate electrode into segments spaced apart from each other in the second direction. The first gate separation pattern has a tensile strain when the MOSFET region is a P-channel. MOSFET (PMOSFET) region. The first gate separation pattern has a compressive strain when the MOSFET region is an N-channel MOSFET (NMOSFET) region.
摘要翻译：半导体器件包括：衬底，其包括由器件隔离层限定的至少一个金属氧化物半导体场效应晶体管（MOSFET）区域，并且具有在MOSFET区域上沿第一方向延伸的有源图案;栅极电极与有源并且沿与第一方向相交的第二方向延伸，以及从平面图观察与MOSFET区域相邻的第一栅极分离图案，并且将栅电极在第二方向上彼此间隔开。当MOSFET区域为P沟道时，第一栅极分离图案具有拉伸应变。 MOSFET（PMOSFET）区域。当MOSFET区域是N沟道MOSFET（NMOSFET）区域时，第一栅极分离图案具有压缩应变。

7. 发明授权

US11545489B2 Semiconductor devices having asymmetrical structures 有权
公开(公告)号：US11545489B2
公开(公告)日：2023-01-03
申请号：US17180989
申请日：2021-02-22
申请人： Samsung Electronics Co., Ltd.
发明人： Junggun You , Sungil Park , Joohee Jung , Sunggi Hur
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/762 , H01L21/768 , H01L29/06 , H01L29/423 , H01L29/786
摘要： A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.

8. 发明授权

US10559673B2 Semiconductor devices having vertical transistors with aligned gate electrodes 有权
公开(公告)号：US10559673B2
公开(公告)日：2020-02-11
申请号：US16284843
申请日：2019-02-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sungil Park , Changhee Kim , Yunil Lee , Mirco Cantoro , Junggun You , Donghun Lee
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10 , H01L21/28 , H01L29/40 , H01L29/423 , H01L29/786 , H01L29/417
摘要： A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

9. 发明申请

US20180248018A1 Semiconductor Devices Having Vertical Transistors with Aligned Gate Electrodes 审中-公开
公开(公告)号：US20180248018A1
公开(公告)日：2018-08-30
申请号：US15664226
申请日：2017-07-31
申请人： Samsung Electronics Co., Ltd.
发明人： Sungil Park , Changhee Kim , Yunil Lee , Mirco Cantoro , Junggun You , Donghun Lee
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10 , H01L21/28 , H01L29/40
CPC分类号： H01L29/66666 , H01L21/28114 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/401 , H01L29/4238 , H01L29/66553 , H01L29/7827
摘要： A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

10. 发明申请

US20140203348A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140203348A1
公开(公告)日：2014-07-24
申请号：US14162481
申请日：2014-01-23
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Dae Suk , Heesoo Kang , Sungil Park , Changwoo Oh
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L21/764 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.
摘要翻译：提供了一种半导体器件，其包括跨越设置在衬底上的半导体翅片上的栅极电极，设置在栅极电极和半导体鳍片之间的栅极电介质层，具有限定在半导体鳍片下方的三维结构的沟道区域栅极电极，设置在栅电极两侧并与栅电极间隔开的半导体鳍片中的杂质区域，除了栅电极之外覆盖基板整个表面的第一层间电介质层，穿过第第一层间电介质层和与杂质区接触的第二层间电介质层和覆盖栅电极并部分地填充栅电极和杂质区之间的空间的第二层间电介质层，以限定栅电极和杂质区之间的气隙。

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