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1. 发明授权

US09559102B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09559102B2
公开(公告)日：2017-01-31
申请号：US14976105
申请日：2015-12-21
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yoonhae Kim , Myungil Kang , Sooyeon Jeong
IPC分类号： H01L29/78 , H01L27/092 , H01L27/088
CPC分类号： H01L27/0922 , H01L21/823425 , H01L21/823431 , H01L21/823814 , H01L21/823821 , H01L27/0207 , H01L27/0886 , H01L27/0924 , H01L29/785
摘要： A semiconductor device includes first and second active regions. Each active region includes a plurality of fin protrusions and a recessed area disposed between the fin protrusions. A plurality of gate structures are disposed on each of the plurality of fin protrusions. A semiconductor layer is disposed in each recessed area. A distance between the gate structures of the first active region is the same as a distance between the gate structures of the second active region, and a height difference between a bottom surface of the semiconductor layer of the first recessed area and a top surface of each of the fin protrusions of the first active region is smaller than a height difference between a bottom surface of the semiconductor layer of the recessed area of the second active region and a top surface of each of the fin protrusions of the second active region.
摘要翻译：半导体器件包括第一和第二有源区。每个有源区域包括多个翅片突出部和设置在翅片突出部之间的凹陷区域。多个栅极结构设置在多个翅片突起中的每一个上。半导体层设置在每个凹陷区域中。第一有源区域的栅极结构之间的距离与第二有源区域的栅极结构之间的距离与第一凹入区域的半导体层的底表面和每个第一有源区域的顶表面之间的高度差相同第一有源区的鳍突起的距离小于第二有源区的凹陷区域的半导体层的底表面和第二有源区的每个鳍突起的顶表面之间的高度差。

2. 发明授权

US09337112B2 Semiconductor device having test structure 有权
公开(公告)号：US09337112B2
公开(公告)日：2016-05-10
申请号：US14725603
申请日：2015-05-29
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ping Hsun Su , Yoonhae Kim , Hwasung Rhee
IPC分类号： H01L21/8234 , H01L21/66
CPC分类号： H01L22/34
摘要： A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

3. 发明申请

US20140210017A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20140210017A1
公开(公告)日：2014-07-31
申请号：US14243358
申请日：2014-04-02
申请人： Samsung Electronics Co., Ltd.
发明人： Myeongcheol Kim , Sooyeon Jeong , Joon Goo Hong , Dohyoung Kim , Yongjin Kim , Jin Wook Lee , Yoonhae Kim
IPC分类号： H01L29/49
CPC分类号： H01L29/4966 , H01L21/76804 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L29/4958 , H01L29/4975 , H01L29/66545
摘要： A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes.
摘要翻译：半导体器件和形成半导体器件的方法包括：在半导体衬底上形成栅电极并在栅电极的两个侧表面上形成间隔物; 在栅电极上形成封盖图案; 以及在栅电极之间形成金属接触。每个封盖图案形成为具有大于每个栅电极的宽度的宽度。

4. 发明授权

US11133392B2 Semiconductor device 有权
公开(公告)号：US11133392B2
公开(公告)日：2021-09-28
申请号：US16243564
申请日：2019-01-09
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hyoseok Choi , Hwichan Jun , Yoonhae Kim , Chulsung Kim , Heungsik Park , Doo-Young Lee
IPC分类号： H01L29/417 , H01L29/78 , H01L29/66
摘要： Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

5. 发明授权

US09882004B2 Semiconductor device having asymmetrical source/drain 有权
公开(公告)号：US09882004B2
公开(公告)日：2018-01-30
申请号：US15423406
申请日：2017-02-02
申请人： Samsung Electronics Co., Ltd.
发明人： Jongki Jung , Myungil Kang , Yoonhae Kim , Kwanheum Lee
IPC分类号： H01L21/8234 , H01L29/08 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/0653 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/7848 , H01L29/7851
摘要： A semiconductor device includes a substrate, an active fin protruding from the substrate, and an asymmetric diamond-shaped source/drain disposed on an upper surface of the active fin. The source/drain includes a first crystal growth portion and a second crystal growth portion sharing a plane with the first crystal growth portion and having a lower surface disposed at a lower level than a lower surface of the first crystal growth portion.

6. 发明授权

US09691902B2 Semiconductor device 有权
公开(公告)号：US09691902B2
公开(公告)日：2017-06-27
申请号：US14990398
申请日：2016-01-07
申请人： Samsung Electronics Co., Ltd.
发明人： Myungil Kang , Yoonhae Kim , Byeongchan Lee
IPC分类号： H01L29/78 , H01L29/417 , H01L27/092 , H01L29/423
CPC分类号： H01L29/7848 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L27/0924 , H01L29/41725 , H01L29/4232 , H01L29/785
摘要： A semiconductor device includes a first pattern on a first active region, a second pattern on a second active region, and a third pattern on a third active region. The first pattern is spaced from the second pattern by a first interval corresponding to the width of a first recess between the first and second active regions. The second pattern is spaced from the third pattern by a second interval corresponding to the width of a second recess between the second and third active regions. The first, second, and third patterns includes gate patterns, and the first and second recesses include semiconductor material with a conductivity type different from the active regions. The semiconductor material in one recess extends higher than the semiconductor material in the other recess. The first, second, and third patterns have the same width, and the first and second recesses have different depths.

7. 发明申请

US20160365274A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制备半导体器件的方法
公开(公告)号：US20160365274A1
公开(公告)日：2016-12-15
申请号：US15145924
申请日：2016-05-04
申请人： Samsung Electronics Co., Ltd.
发明人： Kyungin Choi , Jaeran Jang , Yoonhae Kim
IPC分类号： H01L21/768 , H01L29/08 , H01L29/16 , H01L27/11 , H01L29/165 , H01L29/78 , H01L29/66 , H01L21/8238 , H01L29/06 , H01L29/161
CPC分类号： H01L21/76825 , H01L21/31155 , H01L21/76805 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L21/823878 , H01L27/1104 , H01L27/1116 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/7848
摘要： Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅极图案，形成间隔物以覆盖栅极图案的两个侧壁，形成层间绝缘层以覆盖栅极图案和间隔物，并形成穿透层间绝缘层的接触孔并暴露间隔物的侧壁。间隔件的形成包括形成间隔层以覆盖栅极图案并将硅离子注入间隔层。间隔层是介电常数低于氧化硅的介电常数的氮化物基低k绝缘层。

8. 发明授权

US09349851B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US09349851B2
公开(公告)日：2016-05-24
申请号：US14140616
申请日：2013-12-26
申请人： Samsung Electronics Co., Ltd.
发明人： Yoonhae Kim , Hong Seong Kang , Junjie Xiong , Yoonseok Lee , Youshin Choi
IPC分类号： H01L29/66 , H01L29/78 , H01L29/49 , H01L21/8234 , H01L29/51
CPC分类号： H01L29/78 , H01L21/823468 , H01L21/823475 , H01L29/4966 , H01L29/51 , H01L29/66545
摘要： A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.
摘要翻译：半导体器件包括具有有源区和限定有源区的器件隔离层的衬底，有源区上的栅电极，栅电极两侧的有源区的源/漏区，器件隔离层，形成在缓冲绝缘层上并延伸到栅电极和源极/漏极区的蚀刻停止层，在蚀刻停止层上的第一层间绝缘层，第一接触和穿过第一层间绝缘的第二接触层和蚀刻停止层。第一触点和第二触点彼此间隔开并分别与源极/漏极区域和缓冲绝缘层接触。

9. 发明授权

US11322590B2 Semiconductor device having asymmetrical source/drain 有权
公开(公告)号：US11322590B2
公开(公告)日：2022-05-03
申请号：US16875314
申请日：2020-05-15
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jongki Jung , Myungil Kang , Yoonhae Kim , Kwanheum Lee
IPC分类号： H01L29/08 , H01L29/161 , H01L29/16 , H01L29/165 , H01L29/78 , H01L29/06 , H01L21/8234 , H01L27/088 , H01L29/66
摘要： A semiconductor device includes a substrate, a first active fin on the substrate, the first active fin including a first side surface and a second side surface opposing the first side surface, a second active fin on the substrate, the second active fin including a third side surface facing the second side surface and a fourth side surface opposing the third side surface of the second active fin, a first isolation layer on the first side surface of the first active fin, a second isolation layer between the second side surface of the first active fin and the third side surface of the second active fin, a third isolation layer on the fourth side surface of the second active fin and a merged source/drain on the first and second active fins.

10. 发明授权

US10658463B2 Semiconductor device having asymmetrical source/drain 有权
公开(公告)号：US10658463B2
公开(公告)日：2020-05-19
申请号：US15880969
申请日：2018-01-26
申请人： Samsung Electronics Co., Ltd.
发明人： Jongki Jung , Myungil Kang , Yoonhae Kim , Kwanheum Lee
IPC分类号： H01L21/8234 , H01L29/08 , H01L29/161 , H01L29/16 , H01L29/165 , H01L29/78 , H01L29/06 , H01L27/088 , H01L29/66
摘要： A semiconductor device includes a substrate, an active fin protruding from the substrate, and an asymmetric diamond-shaped source/drain disposed on an upper surface of the active fin. The source/drain includes a first crystal growth portion and a second crystal growth portion sharing a plane with the first crystal growth portion and having a lower surface disposed at a lower level than a lower surface of the first crystal growth portion.

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