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1. 发明授权

US10381370B2 Semiconductor device 有权
公开(公告)号：US10381370B2
公开(公告)日：2019-08-13
申请号：US15869888
申请日：2018-01-12
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yoo-cheol Shin , Young-woo Park , Jae-duk Lee
IPC分类号： H01L51/00 , H01L27/11578 , H01L27/11526 , H01L27/11573 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66 , H01L29/788 , H01L29/792 , H01L27/1157
摘要： A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

2. 发明授权

US09355969B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US09355969B2
公开(公告)日：2016-05-31
申请号：US14723721
申请日：2015-05-28
申请人： Samsung Electronics Co., Ltd.
发明人： Young-woo Park
IPC分类号： H01L23/552 , H01L23/58 , H01L23/522 , H01L23/528 , H01L25/065
CPC分类号： H01L23/58 , H01L23/3128 , H01L23/49816 , H01L23/5226 , H01L23/5286 , H01L23/5384 , H01L23/552 , H01L25/0657 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor package includes a package substrate including a ground pad; a a conductive spacer and a first semiconductor chip disposed on the package substrate; a second semiconductor chip on the conductive spacer and the first semiconductor chip; a molding unit that covers the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the conductive spacer, and exposes a second portion of the conductive spacer; and an electromagnetic interference (EMI) shield that covers the molding unit.
摘要翻译：半导体封装包括包括接地焊盘的封装基板; 导电间隔物和设置在封装基板上的第一半导体芯片; 导电间隔物和第一半导体芯片上的第二半导体芯片; 覆盖所述封装基板，所述第一半导体芯片，所述第二半导体芯片和所述导电间隔物的第一部分的模制单元，并且暴露所述导电间隔物的第二部分; 以及覆盖模制单元的电磁干扰（EMI）屏蔽。

3. 发明申请

US20160071810A1 SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体封装
公开(公告)号：US20160071810A1
公开(公告)日：2016-03-10
申请号：US14723721
申请日：2015-05-28
申请人： Samsung Electronics Co., Ltd.
发明人： Young-woo Park
IPC分类号： H01L23/58 , H01L23/528 , H01L25/065 , H01L23/522
CPC分类号： H01L23/58 , H01L23/3128 , H01L23/49816 , H01L23/5226 , H01L23/5286 , H01L23/5384 , H01L23/552 , H01L25/0657 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor package includes a package substrate including a ground pad; a a conductive spacer and a first semiconductor chip disposed on the package substrate; a second semiconductor chip on the conductive spacer and the first semiconductor chip; a molding unit that covers the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the conductive spacer, and exposes a second portion of the conductive spacer; and an electromagnetic interference (EMI) shield that covers the molding unit.
摘要翻译：半导体封装包括包括接地焊盘的封装基板; 导电间隔物和设置在封装基板上的第一半导体芯片; 导电间隔物和第一半导体芯片上的第二半导体芯片; 覆盖所述封装基板，所述第一半导体芯片，所述第二半导体芯片和所述导电间隔物的第一部分的模制单元，并且暴露所述导电间隔物的第二部分; 以及覆盖模制单元的电磁干扰（EMI）屏蔽。

4. 发明授权

US10903226B2 Semiconductor device 有权
公开(公告)号：US10903226B2
公开(公告)日：2021-01-26
申请号：US16844064
申请日：2020-04-09
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yoo-cheol Shin , Young-woo Park , Jae-duk Lee
IPC分类号： H01L27/11578 , H01L27/11526 , H01L27/11573 , H01L27/11551 , H01L27/11556 , H01L29/66 , H01L29/788 , H01L29/792 , H01L27/11582 , H01L27/1157
摘要： A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

5. 发明申请

US20190252401A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190252401A1
公开(公告)日：2019-08-15
申请号：US16396027
申请日：2019-04-26
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yoo-cheol Shin , Young-woo Park , Jae-duk Lee
IPC分类号： H01L27/11578 , H01L27/1157 , H01L29/792 , H01L29/788 , H01L29/66 , H01L27/11551 , H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11526
CPC分类号： H01L27/11578 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

6. 发明授权

US09620511B2 Vertical semiconductor device 有权
公开(公告)号：US09620511B2
公开(公告)日：2017-04-11
申请号：US14267909
申请日：2014-05-02
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-goo Lee , Young-woo Park , Jin-taek Park
IPC分类号： H01L29/66 , H01L21/336 , H01L27/112 , H01L29/78 , H01L29/788 , H01L29/792 , H01L27/1157 , H01L27/11582 , H01L27/11524 , H01L27/11556
CPC分类号： H01L27/11582 , H01L23/5226 , H01L27/11273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/785 , H01L29/7889 , H01L29/7926
摘要： A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.

7. 发明授权

US09905570B2 Semiconductor device with vertical memory 有权
公开(公告)号：US09905570B2
公开(公告)日：2018-02-27
申请号：US15018477
申请日：2016-02-08
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yoo-cheol Shin , Young-woo Park , Jae-duk Lee
IPC分类号： G06K9/00 , H01L27/11578 , H01L27/11526 , H01L27/11573 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66 , H01L29/788 , H01L29/792 , H01L27/1157
CPC分类号： H01L27/11578 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

8. 发明授权

US09899412B2 Vertical semiconductor device 有权
公开(公告)号：US09899412B2
公开(公告)日：2018-02-20
申请号：US15464983
申请日：2017-03-21
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-goo Lee , Young-woo Park , Jin-taek Park
IPC分类号： H01L29/66 , H01L21/336 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L23/522
CPC分类号： H01L27/11582 , H01L23/5226 , H01L27/11273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/785 , H01L29/7889 , H01L29/7926
摘要： A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.

9. 发明申请

US20170194347A1 VERTICAL SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20170194347A1
公开(公告)日：2017-07-06
申请号：US15464983
申请日：2017-03-21
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-goo Lee , Young-woo Park , Jin-taek Park
IPC分类号： H01L27/11582 , H01L23/522 , H01L27/1157 , H01L27/11524 , H01L27/11556
CPC分类号： H01L27/11582 , H01L23/5226 , H01L27/11273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/785 , H01L29/7889 , H01L29/7926
摘要： A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.

10. 发明授权

US09171729B2 Methods of manufacturing vertical semiconductor devices 有权
标题翻译：制造垂直半导体器件的方法
公开(公告)号：US09171729B2
公开(公告)日：2015-10-27
申请号：US14200680
申请日：2014-03-07
申请人： Samsung Electronics Co., Ltd.
发明人： Byung-Kwan You , Kwang-Soo Seol , Young-woo Park , Jin-Soo Lim
IPC分类号： H01L21/20 , H01L21/36 , H01L21/28 , H01L27/115 , H01L29/792 , H01L21/02
CPC分类号： H01L21/28282 , H01L21/02104 , H01L27/11582 , H01L29/7926
摘要： Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.
摘要翻译：制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。第一开口可能暴露基板。可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。可以部分去除牺牲层和绝缘夹层以形成第二开口。可以去除牺牲层以在绝缘夹层之间形成凹槽。控制栅电极可以形成在凹槽中。

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