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1. 发明授权

US09825051B2 Three dimensional NAND device containing fluorine doped layer and method of making thereof 有权
公开(公告)号：US09825051B2
公开(公告)日：2017-11-21
申请号：US14521050
申请日：2014-10-22
申请人： SanDisk Technologies, Inc.
发明人： Peter Rabkin , Jayavel Pachamuthu , Johann Alsmeier
IPC分类号： H01L27/115 , H01L27/11582 , H01L21/28 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/167 , H01L29/423 , H01L29/51 , H01L29/788 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/02131 , H01L21/0214 , H01L21/0217 , H01L21/02178 , H01L21/02274 , H01L21/0228 , H01L21/02321 , H01L21/02326 , H01L21/02337 , H01L21/0234 , H01L21/28282 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/167 , H01L29/42364 , H01L29/51 , H01L29/518 , H01L29/7883
摘要： A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film in the at least one front side opening. The method also includes forming a semiconductor channel in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere.

2. 发明授权

US09530506B2 NAND boosting using dynamic ramping of word line voltages 有权
标题翻译：使用字线电压的动态斜坡进行NAND升压
公开(公告)号：US09530506B2
公开(公告)日：2016-12-27
申请号：US14550897
申请日：2014-11-21
申请人： SanDisk Technologies Inc.
发明人： Peter Rabkin , Yingda Dong , Masaaki Higashitani
IPC分类号： G11C7/00 , G11C16/10 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.
摘要翻译：描述了用于在存储器阵列内的存储器单元的编程期间改进信道增强和减少编程干扰的方法。存储器阵列可以包括NAND快闪存储器结构，诸如垂直NAND结构或位成本可缩放（BiCS）NAND结构。在一些情况下，通过在编程操作期间或整个编程操作期间对未选择的字线施加连续电压斜坡，可以提高与编程禁止的存储器单元相关联的通道的升压。在一个示例中，可以基于所选择的字线的位置来设置在编程操作期间施加到一组未选择字线（例如，所选字线的相邻字线）的Vpass波形的斜率和定时存储器阵列和存储器阵列内的未选择字线组的位置。

3. 发明申请

US20160358933A1 METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE HAVING A HETEROSTRUCTURE QUANTUM WELL CHANNEL 有权
标题翻译：制造具有异质结构量子阱通道的三维存储器件的方法
公开(公告)号：US20160358933A1
公开(公告)日：2016-12-08
申请号：US14733335
申请日：2015-06-08
申请人： SANDISK TECHNOLOGIES INC.
发明人： Peter Rabkin , Jayavel Pachamuthu , Johann Alsmeier , Masaaki Higashitani
IPC分类号： H01L27/115 , H01L29/12 , H01L29/45 , H01L21/324 , H01L21/28 , H01L29/205 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/0214 , H01L21/0217 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/02546 , H01L21/02584 , H01L21/0262 , H01L21/28282 , H01L27/11573 , H01L29/0649 , H01L29/0657 , H01L29/7788 , H01L29/7789 , H01L29/7926
摘要： A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.
摘要翻译：限制在二维圆柱形区域内的圆柱形约束电子气体可以形成在延伸穿过包括控制栅电极的多个导电层的垂直半导体沟道中。存储器开口中的记忆膜插入在垂直半导体沟道和导电层之间。垂直半导体沟道包括较宽的带隙半导体材料和窄带隙半导体材料。在较宽带隙半导体材料和窄带隙半导体材料之间的界面处形成圆柱形约束电子气。作为二维电子气体，圆柱形约束电子气体可以为垂直半导体通道提供高电荷载流子迁移率，其可有利地用于为三维存储器件提供更高的性能。

4. 发明授权

US09449984B2 Vertical NAND device with low capacitance and silicided word lines 有权
标题翻译：具有低电容和硅化字线的垂直NAND器件
公开(公告)号：US09449984B2
公开(公告)日：2016-09-20
申请号：US14465099
申请日：2014-08-21
申请人： SANDISK TECHNOLOGIES, INC.
发明人： Johann Alsmeier , Peter Rabkin
IPC分类号： H01L29/66 , H01L27/115 , H01L21/28 , H01L21/764 , H01L29/792 , H01L29/49 , H01L29/51
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/764 , H01L27/1157 , H01L29/4933 , H01L29/512 , H01L29/7926
摘要： A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. Each of the plurality of control gate electrodes includes a first edge surface which is substantially free of silicide, the first edge surface facing the semiconductor channel and the at least one charge storage region and a silicide located on remaining surfaces of the control gate electrode.
摘要翻译：一种包括衬底和半导体沟道的三维存储器件。半导体通道的至少一个端部基本上垂直于衬底的主表面延伸。该器件还包括位于半导体通道附近的至少一个电荷存储区域以及具有基本上平行于衬底的主表面延伸的条带形状的多个控制栅极电极。多个控制栅电极至少包括位于第一器件级的第一控制栅电极和位于位于衬底的主表面上方且低于第一器件电平的第二器件电平的第二控制栅电极。多个控制栅电极中的每一个包括基本上不含硅化物的第一边缘表面，面向半导体沟道的第一边缘表面和至少一个电荷存储区域以及位于控制栅电极的剩余表面上的硅化物。

5. 发明授权

US09425299B1 Three-dimensional memory device having a heterostructure quantum well channel 有权
标题翻译：具有异质结构量子阱通道的三维存储器件
公开(公告)号：US09425299B1
公开(公告)日：2016-08-23
申请号：US14733244
申请日：2015-06-08
申请人： SANDISK TECHNOLOGIES INC.
发明人： Peter Rabkin , Jayavel Pachamuthu , Johann Alsmeier , Masaaki Higashitani
IPC分类号： H01L29/778 , H01L27/115 , H01L29/205 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7783 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/205 , H01L29/513 , H01L29/7787 , H01L29/7789 , H01L29/7833 , H01L29/7889
摘要： A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.
摘要翻译：限制在二维圆柱形区域内的圆柱形约束电子气体可以形成在延伸穿过包括控制栅电极的多个导电层的垂直半导体沟道中。存储器开口中的记忆膜插入在垂直半导体沟道和导电层之间。垂直半导体沟道包括较宽的带隙半导体材料和窄带隙半导体材料。在较宽带隙半导体材料和窄带隙半导体材料之间的界面处形成圆柱形约束电子气。作为二维电子气体，圆柱形约束电子气体可以为垂直半导体通道提供高电荷载流子迁移率，其可有利地用于为三维存储器件提供更高的性能。

6. 发明申请

US20160148691A1 NAND Boosting Using Dynamic Ramping of Word Line Voltages 有权
公开(公告)号：US20160148691A1
公开(公告)日：2016-05-26
申请号：US14550897
申请日：2014-11-21
申请人： SanDisk Technologies Inc.
发明人： Peter Rabkin , Yingda Dong , Masaaki Higashitani
IPC分类号： G11C16/10
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.
摘要翻译：描述了用于在存储器阵列内的存储器单元的编程期间改进信道增强和减少编程干扰的方法。存储器阵列可以包括NAND快闪存储器结构，诸如垂直NAND结构或位成本可缩放（BiCS）NAND结构。在一些情况下，通过在编程操作期间或整个编程操作期间对未选择的字线施加连续电压斜坡，可以提高与编程禁止的存储器单元相关联的通道的升压。在一个示例中，可以基于所选择的字线的位置来设置在编程操作期间施加到一组未选择字线（例如，所选字线的相邻字线）的Vpass波形的斜率和定时存储器阵列和存储器阵列内的未选择字线组的位置。

7. 发明授权

US09331093B2 Three dimensional NAND device with silicon germanium heterostructure channel 有权
标题翻译：具有硅锗异质结构通道的三维NAND器件
公开(公告)号：US09331093B2
公开(公告)日：2016-05-03
申请号：US14505870
申请日：2014-10-03
申请人： SANDISK TECHNOLOGIES INC.
发明人： Peter Rabkin , Jayavel Pachamuthu
IPC分类号： H01L27/115 , H01L29/165 , H01L29/167 , H01L29/04 , H01L21/28 , H01L21/02 , H01L29/10 , H01L29/78 , H01L29/66
CPC分类号： H01L21/28273 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02667 , H01L21/02686 , H01L21/28282 , H01L27/11556 , H01L27/11582 , H01L29/04 , H01L29/1054 , H01L29/165 , H01L29/167 , H01L29/66825 , H01L29/66833 , H01L29/7842 , H01L29/7881 , H01L29/7926
摘要： A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one opening in the stack, forming at least a portion of a memory film in the at least one opening and forming a first portion of a semiconductor channel followed by forming a second portion of the semiconductor channel in the at least one opening. The second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the memory film than the second portion.
摘要翻译：一种制造单片三维NAND串的方法，包括在衬底上形成第一材料和不同于第一材料的第二材料的交替层的堆叠，在堆叠中形成至少一个开口，形成至少一部分在所述至少一个开口中的记忆膜，并形成半导体通道的第一部分，随后在所述至少一个开口中形成所述半导体通道的第二部分。半导体通道的第二部分包括硅和锗，并且比与第二部分更靠近存储膜的位于半导体通道的第一部分相比包含更多的锗。

8. 发明申请

US20150069377A1 3D NON-VOLATILE STORAGE WITH WIDE BAND GAP TRANSISTOR DECODER 有权
标题翻译： 3D非挥发性存储带宽带隙晶体管解码器
公开(公告)号：US20150069377A1
公开(公告)日：2015-03-12
申请号：US14020621
申请日：2013-09-06
申请人： SanDisk Technologies Inc.
发明人： Peter Rabkin , Masaaki Higashitani
IPC分类号： H01L27/12
CPC分类号： H01L27/1225 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L27/1222 , H01L27/1259 , H01L29/42384 , H01L29/785 , H01L29/7869 , H01L29/78696
摘要： Disclosed herein are 3D stacked memory devices having WL select gates that comprises TFTs having bodies formed from a wide band gap semiconductor. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HfInZnO, or ZnInSnO body. The word lines may be formed from metal, such as tungsten. The 3D stacked memory device could have NAND strings. The TFTs may be formed in the word line layer. The TFT has a high drive current, a high breakdown voltage and low leakage current.
摘要翻译：这里公开了具有WL选择栅极的3D堆叠存储器件，其包括具有由宽带隙半导体形成的主体的TFT。宽能带隙半导体可以是诸如金属氧化物半导体的氧化物半导体。例如，这可以是InGaZnO，InZnO，HfInZnO或ZnInSnO体。字线可以由诸如钨的金属形成。 3D堆叠存储器件可以具有NAND串。 TFT可以形成在字线层中。 TFT具有高驱动电流，高击穿电压和低漏电流。

9. 发明申请

US20150054046A1 3D Non-Volatile Memory With Metal Silicide Interconnect 有权
标题翻译： 3D非易失性存储器与金属硅化物互连
公开(公告)号：US20150054046A1
公开(公告)日：2015-02-26
申请号：US14533576
申请日：2014-11-05
申请人： SanDisk Technologies Inc.
发明人： Masaaki Higashitani , Peter Rabkin
IPC分类号： H01L27/115 , H01L23/532 , H01L29/49
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/06 , H01L23/53209 , H01L27/11519 , H01L27/11531 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.
摘要翻译：堆叠的非易失性存储单元阵列包括具有NAND单元的垂直列行的单元区域，以及例如阵列中途并且延伸阵列的长度的互连区域。互连区域包括在绝缘填充的狭缝之间延伸的至少一个金属硅化物互连，并且不包括NAND单元的垂直列。金属硅化物互连可以将电力和控制信号从堆叠下方传递到堆叠之上。金属硅化物互连也可以形成在衬底的周边区域中。接触结构可以从互连的梯形部分延伸到堆叠之上的至少一个上金属层，以完成从堆叠下方的电路到上金属层的导电路径。可以在阵列的平面中提供子阵列，而不需要字线连接和子阵列之间的传输区域。

10. 发明授权

US09634097B2 3D NAND with oxide semiconductor channel 有权
公开(公告)号：US09634097B2
公开(公告)日：2017-04-25
申请号：US14552964
申请日：2014-11-25
申请人： SanDisk Technologies Inc.
发明人： Peter Rabkin , Johann Alsmeier , Masaaki Higashitani
IPC分类号： H01L29/24 , H01L29/423 , H01L27/115 , H01L27/1157 , H01L27/11578 , H01L21/28 , H01L29/66 , H01L29/786 , H01L29/792 , H01L27/11582 , H01L21/02
CPC分类号： H01L29/24 , H01L21/02565 , H01L21/02631 , H01L21/28282 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/4234 , H01L29/66969 , H01L29/7869 , H01L29/7926
摘要： Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The oxide semiconductor may have a crystalline structure. The channel of the vertically-oriented NAND string may be cylindrically shaped. The crystalline structure has an axis that may be aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. The crystalline structure may have a first axis that is aligned parallel to the vertical channel, a second axis that is aligned perpendicular to a surface of the cylindrically shaped channel, etc.

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