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    • 4. 发明授权
    • Multi-level voltage output control circuit and logic gate therefor
    • 多电平电压输出控制电路及逻辑门
    • US07068075B2
    • 2006-06-27
    • US10876419
    • 2004-06-25
    • Dae-Ho Lim
    • Dae-Ho Lim
    • H03K19/094
    • H03K19/0013
    • A multi-level voltage output control circuit selectively outputs one of multi-level power voltages by driving gates of two MOS transistors, which act as switching devices for the multi-level power voltages, with two output signals, the two output signals having complementary phases to each other and generated from two logic gates receiving two input signals which have an identical timing and complementary phases to each other, wherein the two logic gates advance or slow down a rising timing and/or a falling timing of the two output signals by differently adjusting a size of PMOS transistors and that of NMOS transistors, which construct the logic gates, thereby excluding a case in which the two output signals are in a same logic state at the same time.
    • 多电平电压输出控制电路通过用两个输出信号驱动用于多电平电源电压的开关装置的两个MOS晶体管的栅极驱动多级电源电压中的一个,这两个输出信号具有互补相位 从两个逻辑门产生,两个逻辑门接收彼此具有相同定时和互补相位的两个输入信号,其中两个逻辑门通过不同的方式提前或减慢两个输出信号的上升定时和/或下降定时 调整PMOS晶体管的尺寸和构成逻辑门的NMOS晶体管的尺寸,从而排除两个输出信号同时处于相同逻辑状态的情况。
    • 5. 发明申请
    • Multi-level voltage output control circuit and logic gate therefor
    • 多电平电压输出控制电路及逻辑门
    • US20050218932A1
    • 2005-10-06
    • US10876419
    • 2004-06-25
    • Dae-Ho Lim
    • Dae-Ho Lim
    • G09G3/36G09G3/20H03K17/00H03K17/16H03K17/687H03K19/00H03K19/0175H03K19/0948
    • H03K19/0013
    • A multi-level voltage output control circuit selectively outputs one of multi-level power voltages by driving gates of two MOS transistors, which act as switching devices for the multi-level power voltages, with two output signals, the two output signals having complementary phases to each other and generated from two logic gates receiving two input signals which have an identical timing and complementary phases to each other, wherein the two logic gates advance or slow down a rising timing and/or a falling timing of the two output signals by differently adjusting a size of PMOS transistors and that of NMOS transistors, which construct the logic gates, thereby excluding a case in which the two output signals are in a same logic state at the same time.
    • 多电平电压输出控制电路通过用两个输出信号驱动用于多电平电源电压的开关装置的两个MOS晶体管的栅极驱动多级电源电压中的一个,这两个输出信号具有互补相位 从两个逻辑门产生,两个逻辑门接收彼此具有相同定时和互补相位的两个输入信号,其中两个逻辑门通过不同的方式提前或减慢两个输出信号的上升定时和/或下降定时 调整PMOS晶体管的尺寸和构成逻辑门的NMOS晶体管的尺寸,从而排除两个输出信号同时处于相同逻辑状态的情况。