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1. 发明申请

US20210012855A1 Method and Apparatus for enabling Multiple Return Material Authorizations (RMAs) on an Integrated Circuit Device 有权
公开(公告)号：US20210012855A1
公开(公告)日：2021-01-14
申请号：US17033526
申请日：2020-09-25
申请人： Sankaran M. Menon , Andrew Martyn Draper , Ting Lu , Kenneth Chen , Wei Chun Lau
发明人： Sankaran M. Menon , Andrew Martyn Draper , Ting Lu , Kenneth Chen , Wei Chun Lau
IPC分类号： G11C29/44 , G11C29/38 , G11C29/16 , G11C17/14
摘要： An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse.

2. 发明申请

US20140006836A1 Observing Embedded Signals Of Varying Clock Domains 有权
标题翻译：观察不同时钟域的嵌入式信号
公开(公告)号：US20140006836A1
公开(公告)日：2014-01-02
申请号：US13536148
申请日：2012-06-28
申请人： Sankaran M. Menon , Binta M. Patel , Bo Jiang , Nancy G. Woodbridge
发明人： Sankaran M. Menon , Binta M. Patel , Bo Jiang , Nancy G. Woodbridge
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F1/12
摘要： Observability of internal system-on-chip signals is a difficult problem and it is particularly difficult to observe and debug transactions with different clock domains. However, one embodiment provides observability of internal signals from multiple internal blocks having varying clock domains such as synchronous (common clock) and asynchronous (non common clock) domains. An embodiment provides simultaneous observability of debug data from both synchronous and asynchronous clock domains. An embodiment may also allow sending debug data from both synchronous and asynchronous domains from the SoC. One embodiment outputs internal signals on output pins of the SoC, thereby allowing transactions from one clock domain to be tracked to another clock domain and allowing for the determination of the relationship between the data of differing clock domains. Other embodiments are described herein.
摘要翻译：内部片上系统信号的可观察性是一个困难的问题，特别难以观察和调试与不同时钟域的交易。然而，一个实施例提供了具有变化的时钟域（例如同步（公共时钟））和异步（非公共时钟）域的多个内部块的内部信号的可观察性。一个实施例提供来自同步和异步时钟域的调试数据的同时可观察性。一个实施例还可以允许从SoC发送来自同步和异步域的调试数据。一个实施例在SoC的输出引脚上输出内部信号，从而允许来自一个时钟域的事务被跟踪到另一个时钟域，并允许确定不同时钟域的数据之间的关系。本文描述了其它实施例。

3. 发明申请

US20130339789A1 METHOD AND APPARATUS FOR OUTPUT OF HIGH-BANDWIDTH DEBUG DATA/TRACES IN ICS AND SOCS USING EMBEDDED HIGH SPEED DEBUG 有权
标题翻译：使用嵌入式高速调试的ICS和SOCS中的高带宽调试数据/跟踪输出的方法和装置
公开(公告)号：US20130339789A1
公开(公告)日：2013-12-19
申请号：US13526211
申请日：2012-06-18
申请人： Sankaran M. Menon , Sridhar K. Valluru , Ramana Rachakonda
发明人： Sankaran M. Menon , Sridhar K. Valluru , Ramana Rachakonda
IPC分类号： G06F11/273
CPC分类号： G06F11/3656 , G06F11/267
摘要： Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces.
摘要翻译：在使用嵌入式高速调试端口的电子设备中输出高带宽调试数据/迹线的方法和装置。调试数据从多个块接收并缓冲在缓冲区中。缓冲器的输出在调试测试操作期间通过复用逻辑可操作地耦合到一个或多个高速串行I / O接口。缓冲数据被编码为串行数据，并通过一个或多个高速串行I / O接口发送到接收串行化数据并将其解串行化以生成提供给调试器的并行调试数据的逻辑设备。缓冲器可以被配置为带宽适配缓冲器，其有助于传输以通过一个或多个高速串行I / O接口以可变组合数据速率出站的调制数据的传输，数据速率是对应于串行I / O接口。

4. 发明授权

US08924786B2 No-touch stress testing of memory I/O interfaces 有权
标题翻译：内存I / O接口的无接触压力测试
公开(公告)号：US08924786B2
公开(公告)日：2014-12-30
申请号：US13536372
申请日：2012-06-28
申请人： Sankaran M. Menon , Robert R. Roeder
发明人： Sankaran M. Menon , Robert R. Roeder
IPC分类号： G06F11/00
CPC分类号： G11C29/022 , G11C11/40 , G11C29/06 , G11C2029/0401 , G11C2029/5602
摘要： Embodiments are generally directed no-touch stress testing of memory input/output (I/O) interfaces. An embodiment of a memory device includes a system element to be coupled with a dynamic random-access memory (DRAM), the system element including a memory interface for connection with the DRAM, the interface including a driver and a receiver, a memory controller for control of the DRAM, and a timing stress testing logic for testing of the I/O interface.
摘要翻译：实施例通常针对存储器输入/输出（I / O）接口的无触摸应力测试。存储器件的实施例包括要与动态随机存取存储器（DRAM）耦合的系统元件，所述系统元件包括用于与DRAM连接的存储器接口，所述接口包括驱动器和接收器，存储器控制器， DRAM的控制，以及测试I / O接口的时序应力测试逻辑。

5. 发明授权

US08904253B2 Method and apparatus for testing I/O boundary scan chain for SoC's having I/O's powered off by default 有权
标题翻译：用于测试I / O边界扫描链的方法和设备，默认情况下，I / O的电源关闭
公开(公告)号：US08904253B2
公开(公告)日：2014-12-02
申请号：US13532108
申请日：2012-06-25
申请人： Sankaran M. Menon , Robert R. Roeder , Liwei E. Ju
发明人： Sankaran M. Menon , Robert R. Roeder , Liwei E. Ju
IPC分类号： G01R31/28 , G06F11/00 , G01R31/3185 , G01R31/319 , G01R31/317 , G06F1/32
CPC分类号： G01R31/318575 , G01R31/2815 , G01R31/31713 , G01R31/31717 , G01R31/318508 , G01R31/318533 , G01R31/318572 , G01R31/318597 , G01R31/31905 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3246 , G06F1/3278 , G06F1/3287
摘要： Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.
摘要翻译：用于测试具有默认关闭电源的I / O的片上系统（SoC）的输入/输出（I / O）边界扫描链的方法和装置。一些方法和装置包括实现边界扫描链路旁路路由方案，其选择性地在围绕I / O接口和/或默认关闭的端口的边界扫描链路径路由。其他技术包括默认情况下，以独立于SoC设施的方式关闭电源的I / O，用于在SoC运行时操作期间控制I / O的电源状态。各种方案有助于根据IEEE标准1149.1方法进行边界扫描测试。

6. 发明授权

US07568141B2 Method and apparatus for testing embedded cores 有权
标题翻译：嵌入式核心测试方法和装置
公开(公告)号：US07568141B2
公开(公告)日：2009-07-28
申请号：US11963689
申请日：2007-12-21
申请人： Sankaran M. Menon , Luis A. Basto , Tien Dinh , Thomas Tomazin , Juan G. Revilla
发明人： Sankaran M. Menon , Luis A. Basto , Tien Dinh , Thomas Tomazin , Juan G. Revilla
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/318508 , G01R31/318513 , G01R31/318541 , G01R31/318555 , G11C2029/0401 , G11C2029/3202
摘要： The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.
摘要翻译：嵌入式核心（例如核心终端）的输入可能不直接连接到SoC上的引脚。直接访问嵌入式核心终端的可能会使嵌入式核心的测试复杂化。可以使用包括边界扫描测试（BST）单元的测试包装器来测试嵌入式核心。双功能BST / ATPG（自动测试模式生成）单元可用于对嵌入式核心执行BST和ATPG测试。

7. 发明授权

US09043649B2 Method and apparatus for output of high-bandwidth debug data/traces in ICS and SoCs using embedded high speed debug 有权
标题翻译：使用嵌入式高速调试在ICS和SoC中输出高带宽调试数据/迹线的方法和装置
公开(公告)号：US09043649B2
公开(公告)日：2015-05-26
申请号：US13526211
申请日：2012-06-18
申请人： Sankaran M. Menon , Sridhar K. Valluru , Ramana Rachakonda
发明人： Sankaran M. Menon , Sridhar K. Valluru , Ramana Rachakonda
IPC分类号： G06F11/36
CPC分类号： G06F11/3656 , G06F11/267
摘要： Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces.
摘要翻译：在使用嵌入式高速调试端口的电子设备中输出高带宽调试数据/迹线的方法和装置。调试数据从多个块接收并缓冲在缓冲区中。缓冲器的输出在调试测试操作期间通过复用逻辑可操作地耦合到一个或多个高速串行I / O接口。缓冲数据被编码为串行数据，并通过一个或多个高速串行I / O接口发送到接收串行化数据并将其解串行化以生成提供给调试器的并行调试数据的逻辑设备。缓冲器可以被配置为带宽适配缓冲器，其有助于传输以通过一个或多个高速串行I / O接口以可变组合数据速率出站的调制数据的传输，数据速率是对应于串行I / O接口。

8. 发明申请

US20130346816A1 METHOD AND APPARATUS FOR TESTING I/O BOUNDARY SCAN CHAIN FOR SOC'S HAVING I/O'S POWERED OFF BY DEFAULT 有权
标题翻译：用于测试I / O边界扫描链的方法和装置，用于具有缺省I / O的I / O的SOC
公开(公告)号：US20130346816A1
公开(公告)日：2013-12-26
申请号：US13532108
申请日：2012-06-25
申请人： Sankaran M. Menon , Robert R. Roeder , Liwei E. Ju
发明人： Sankaran M. Menon , Robert R. Roeder , Liwei E. Ju
IPC分类号： G01R31/3177
CPC分类号： G01R31/318575 , G01R31/2815 , G01R31/31713 , G01R31/31717 , G01R31/318508 , G01R31/318533 , G01R31/318572 , G01R31/318597 , G01R31/31905 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3246 , G06F1/3278 , G06F1/3287
摘要： Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.
摘要翻译：用于测试具有默认关闭电源的I / O的片上系统（SoC）的输入/输出（I / O）边界扫描链的方法和装置。一些方法和装置包括实现边界扫描链路旁路路由方案，其选择性地在围绕I / O接口和/或默认关闭的端口的边界扫描链路径路由。其他技术包括默认情况下，以独立于SoC设施的方式关闭电源的I / O，用于在SoC运行时操作期间控制I / O的电源状态。各种方案有助于根据IEEE标准1149.1方法进行边界扫描测试。

9. 发明授权

US07313739B2 Method and apparatus for testing embedded cores 有权
标题翻译：嵌入式核心测试方法和装置
公开(公告)号：US07313739B2
公开(公告)日：2007-12-25
申请号：US10335149
申请日：2002-12-31
申请人： Sankaran M. Menon , Luis A. Basto , Tien Dinh , Thomas Tomazin , Juan G. Revilla
发明人： Sankaran M. Menon , Luis A. Basto , Tien Dinh , Thomas Tomazin , Juan G. Revilla
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G01R31/318508 , G01R31/318513 , G01R31/318541 , G01R31/318555 , G11C2029/0401 , G11C2029/3202
摘要： Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an address of said memory element in a storage unit.
摘要翻译：测试存储设备。装置可以包括可操作以对多个流水线存储器元件执行测试的测试模块和响应于识别存储器元件的故障并且将所述存储器元件的地址存储在存储器元件中的操作来中断测试的故障跟踪模块存储单元。

10. 发明申请

US20140006864A1 NO-TOUCH STRESS TESTING OF MEMORY I/O INTERFACES 有权
标题翻译：存储器I / O接口的无触摸应力测试
公开(公告)号：US20140006864A1
公开(公告)日：2014-01-02
申请号：US13536372
申请日：2012-06-28
申请人： Sankaran M. Menon , Robert R. Roeder
发明人： Sankaran M. Menon , Robert R. Roeder
IPC分类号： G06F11/28
CPC分类号： G11C29/022 , G11C11/40 , G11C29/06 , G11C2029/0401 , G11C2029/5602
摘要： Embodiments are generally directed no-touch stress testing of memory input/output (I/O) interfaces. An embodiment of a memory device includes a system element to be coupled with a dynamic random-access memory (DRAM), the system element including a memory interface for connection with the DRAM, the interface including a driver and a receiver, a memory controller for control of the DRAM, and a timing stress testing logic for testing of the I/O interface.
摘要翻译：实施例通常针对存储器输入/输出（I / O）接口的无触摸应力测试。存储器件的实施例包括要与动态随机存取存储器（DRAM）耦合的系统元件，所述系统元件包括用于与DRAM连接的存储器接口，所述接口包括驱动器和接收器，存储器控制器， DRAM的控制，以及测试I / O接口的时序应力测试逻辑。

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