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    • 8. 发明授权
    • Cache line pre-load and pre-own based on cache coherence speculation
    • 缓存线预加载和基于缓存一致性推测的预先拥有
    • US06725341B1
    • 2004-04-20
    • US09605239
    • 2000-06-28
    • Jih-Kwon PeirSteve Y. ZhangScott H. RobinsonKonrad LaiWen-Hann Wang
    • Jih-Kwon PeirSteve Y. ZhangScott H. RobinsonKonrad LaiWen-Hann Wang
    • G06F1200
    • G06F12/0831
    • The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.
    • 本发明提供一种缓存管理系统,其包括在各种实施例中预先加载和预先拥有的功能,以增强共享存储器分布式高速缓存多处理器计算机系统中的高速缓存效率。 本发明的一些实施例包括无效历史表,用于记录通过脏或无效无效而无效的高速缓存行的行地址,并且其被使用,使得记录在无效历史表中的无效高速缓存行通过监视高速缓存的总线被重新加载到高速缓存中 记录在无效历史表中的高速缓存行的行地址。 在一些另外的实施例中,与每个L2高速缓存条目相关联的回写位在检测到另一个处理器中的同一行的命中时或者当另一个处理器的高速缓存中的同一行无效时记录,并且系统广播回写从 所选择的本地缓存只有当正在写回的行具有已设置的回写位时。
    • 10. 发明授权
    • Processsor integral technologies for BIOS flash attack protection and notification
    • 用于BIOS闪存攻击保护和通知的进程集成技术
    • US09015455B2
    • 2015-04-21
    • US13178338
    • 2011-07-07
    • James P. HeldScott H. RobinsonVincent J. Zimmer
    • James P. HeldScott H. RobinsonVincent J. Zimmer
    • G06F9/00G06F21/57G06F9/44
    • G06F21/575G06F9/4401G06F21/64
    • A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.
    • 用于BIOS闪存防护和通知的系统和方法。 包括初始化固件验证模块的处理器初始化模块可以被配置为响应于电源接通和/或复位而首先执行并且验证处理器封装中存储在非易失性存储器中的初始化固件。 初始化固件配置为验证BIOS。 如果初始化固件和/或BIOS的验证失败,则系统被配置为选择多个响应中的至少一个,包括但不限于防止BIOS执行,启动恢复,报告验证失败,停止 ,关闭和/或允许BIOS执行,以及操作系统(OS)以有限的功能模式进行引导。