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1. 发明申请

US20060131756A1 Semiconductor device with a metal line and method of forming the same 失效
公开(公告)号：US20060131756A1
公开(公告)日：2006-06-22
申请号：US11304771
申请日：2005-12-16
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76808 , H01L21/7681
摘要： A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop layer; forming a second insulation layer and a second etch stop layer on the first insulation layer and the first etch stop layer, and forming a second photosensitive layer pattern on the second etch stop layer; forming a second opening by etching the second etch stop layer; simultaneously forming an inter-connection groove and a via hole by etching the first insulation layer and the second insulation layer using the second etch stop layer and the first etch stop layer as a mask; and forming a metal line by filling the inter-connection groove and the via hole with conductive materials.

2. 发明授权

US07977770B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07977770B2
公开(公告)日：2011-07-12
申请号：US12155903
申请日：2008-06-11
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L23/528 , H01L23/535
CPC分类号： H01L24/05 , H01L21/78 , H01L22/34 , H01L24/03 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05624 , H01L2224/05647 , H01L2224/45144 , H01L2224/4554 , H01L2224/45669 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.
摘要翻译：一种制造半导体器件的方法包括：在划线区域中形成包括第一金属的第一焊盘和包括第一金属的连接线; 在芯片区域中形成包括第一金属的第二焊盘; 在第一焊盘，连接间连接线和第二焊盘上依次形成蚀刻停止层和第一绝缘层; 通过图案化蚀刻停止层和第一绝缘层来暴露第一和第二焊盘; 在所述第一和第二焊盘上形成包括第二金属的第三和第四焊盘; 在第三焊盘，第四焊盘和图案化的第一绝缘层上依次形成第二和第三绝缘层; 以及使用所述第三绝缘层上的所述图案化感光层蚀刻所述第一绝缘层，所述第二绝缘层和所述第三绝缘层以暴露所述第三和第四焊盘

3. 发明授权

US07618887B2 Semiconductor device with a metal line and method of forming the same 失效
标题翻译：具有金属线的半导体器件及其形成方法
公开(公告)号：US07618887B2
公开(公告)日：2009-11-17
申请号：US11304771
申请日：2005-12-16
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L21/20
CPC分类号： H01L21/76831 , H01L21/76808 , H01L21/7681
摘要： A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop layer; forming a second insulation layer and a second etch stop layer on the first insulation layer and the first etch stop layer, and forming a second photosensitive layer pattern on the second etch stop layer; forming a second opening by etching the second etch stop layer; simultaneously forming an inter-connection groove and a via hole by etching the first insulation layer and the second insulation layer using the second etch stop layer and the first etch stop layer as a mask; and forming a metal line by filling the inter-connection groove and the via hole with conductive materials.
摘要翻译：一种在半导体器件中形成金属线的方法，包括在导电层上形成第一绝缘层和第一蚀刻停止层，以及在第一蚀刻停止层上形成第一感光层图案; 通过蚀刻第一蚀刻停止层形成第一开口; 在第一绝缘层和第一蚀刻停止层上形成第二绝缘层和第二蚀刻停止层，以及在第二蚀刻停止层上形成第二感光层图案; 通过蚀刻第二蚀刻停止层形成第二开口; 同时通过使用第二蚀刻停止层和第一蚀刻停止层作为掩模蚀刻第一绝缘层和第二绝缘层来形成互连槽和通孔; 并通过用导电材料填充连接槽和通孔来形成金属线。

4. 发明授权

US07399698B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07399698B2
公开(公告)日：2008-07-15
申请号：US11320697
申请日：2005-12-30
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L21/4763 , H01L21/283 , H01L21/311 , H01L21/441
CPC分类号： H01L24/05 , H01L21/78 , H01L22/34 , H01L24/03 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05624 , H01L2224/05647 , H01L2224/45144 , H01L2224/4554 , H01L2224/45669 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.
摘要翻译：一种制造半导体器件的方法包括：在划线区域中形成包括第一金属的第一焊盘和包括第一金属的连接线; 在芯片区域中形成包括第一金属的第二焊盘; 在第一焊盘，连接间连接线和第二焊盘上依次形成蚀刻停止层和第一绝缘层; 通过图案化蚀刻停止层和第一绝缘层来暴露第一和第二焊盘; 在所述第一和第二焊盘上形成包括第二金属的第三和第四焊盘; 在第三焊盘，第四焊盘和图案化的第一绝缘层上依次形成第二和第三绝缘层; 以及使用所述第三绝缘层上的所述图案化感光层蚀刻所述第一绝缘层，所述第二绝缘层和所述第三绝缘层以暴露所述第三和第四焊盘

5. 发明授权

US07745266B2 Method of forming a fuse part 失效
标题翻译：形成保险丝部件的方法
公开(公告)号：US07745266B2
公开(公告)日：2010-06-29
申请号：US11318637
申请日：2005-12-28
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device with a fuse part and a method of forming the same. The method includes forming a selective metal layer on a via hole which is connected to a metal line in a semiconductor device, forming a fuse metal layer on the selective metal layer, and forming a fuse metal layer pattern by using a photosensitive layer pattern which is formed on the fuse metal layer.
摘要翻译：本发明提供一种具有熔丝部分的半导体器件及其形成方法。该方法包括在通孔上形成选择性金属层，所述通孔与半导体器件中的金属线连接，在选择性金属层上形成熔丝金属层，并通过使用感光层图案形成熔丝金属层图案，该感光层图案是形成在熔丝金属层上。

6. 发明申请

US20070194448A1 Semiconductor interconnection line and method of forming the same 有权
标题翻译：半导体互连线及其形成方法
公开(公告)号：US20070194448A1
公开(公告)日：2007-08-23
申请号：US11788794
申请日：2007-04-20
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L23/48
CPC分类号： H01L21/76808 , H01L21/76807 , H01L21/76834 , H01L21/76895
摘要： An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.
摘要翻译：公开了一种半导体器件的互连线及其使用双镶嵌工艺形成该半导体器件的方法。半导体器件的示例性互连线包括半导体衬底，形成在衬底上的第一互连线，形成在衬底上以暴露第一互连线的一部分的绝缘层图案，以及形成在暴露部分上的金属衬垫层的第一条互连线。示例性互连线还包括形成在基板的整个表面上并具有暴露金属焊盘层的通孔和沟槽的中间绝缘层，以及形成在通孔和沟槽中的电连接到第一互连线通过金属焊盘层。

7. 发明申请

US20060163700A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060163700A1
公开(公告)日：2006-07-27
申请号：US11320697
申请日：2005-12-30
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L23/544
CPC分类号： H01L24/05 , H01L21/78 , H01L22/34 , H01L24/03 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05624 , H01L2224/05647 , H01L2224/45144 , H01L2224/4554 , H01L2224/45669 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.
摘要翻译：一种制造半导体器件的方法包括：在划线区域中形成包括第一金属的第一焊盘和包括第一金属的连接线; 在芯片区域中形成包括第一金属的第二焊盘; 在第一焊盘，连接间连接线和第二焊盘上依次形成蚀刻停止层和第一绝缘层; 通过图案化蚀刻停止层和第一绝缘层来暴露第一和第二焊盘; 在所述第一和第二焊盘上形成包括第二金属的第三和第四焊盘; 在第三焊盘，第四焊盘和图案化的第一绝缘层上依次形成第二和第三绝缘层; 以及使用所述第三绝缘层上的所述图案化感光层蚀刻所述第一绝缘层，所述第二绝缘层和所述第三绝缘层以暴露所述第三和第四焊盘。

8. 发明申请

US20050140020A1 Semiconductor interconnection line and method of forming the same 有权
标题翻译：半导体互连线及其形成方法
公开(公告)号：US20050140020A1
公开(公告)日：2005-06-30
申请号：US11026717
申请日：2004-12-30
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L21/28 , H01L21/768 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76808 , H01L21/76807 , H01L21/76834 , H01L21/76895
摘要： An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.
摘要翻译：公开了一种半导体器件的互连线及其使用双镶嵌工艺形成该半导体器件的方法。半导体器件的示例性互连线包括半导体衬底，形成在衬底上的第一互连线，形成在衬底上以暴露第一互连线的一部分的绝缘层图案，以及形成在暴露部分上的金属衬垫层的第一条互连线。示例性互连线还包括形成在基板的整个表面上并具有暴露金属焊盘层的通孔和沟槽的中间绝缘层，以及形成在通孔和沟槽中的电连接到第一互连线通过金属焊盘层。

9. 发明授权

US07960839B2 Semiconductor interconnection line and method of forming the same 有权
标题翻译：半导体互连线及其形成方法
公开(公告)号：US07960839B2
公开(公告)日：2011-06-14
申请号：US11788794
申请日：2007-04-20
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L23/48
CPC分类号： H01L21/76808 , H01L21/76807 , H01L21/76834 , H01L21/76895
摘要： An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.
摘要翻译：公开了一种半导体器件的互连线及其使用双镶嵌工艺形成该半导体器件的方法。半导体器件的示例性互连线包括半导体衬底，形成在衬底上的第一互连线，形成在衬底上以暴露第一互连线的一部分的绝缘层图案，以及形成在暴露部分上的金属衬垫层的第一条互连线。示例性互连线还包括形成在基板的整个表面上并具有暴露金属焊盘层的通孔和沟槽的中间绝缘层，以及形成在通孔和沟槽中的电连接到第一互连线通过金属焊盘层。

10. 发明申请

US20080246156A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20080246156A1
公开(公告)日：2008-10-09
申请号：US12155903
申请日：2008-06-11
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L21/78 , H01L22/34 , H01L24/03 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05624 , H01L2224/05647 , H01L2224/45144 , H01L2224/4554 , H01L2224/45669 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.

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