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1. 发明授权

US08947419B2 Display controller, display device, display system, and method for controlling display device 有权
标题翻译：显示控制器，显示装置，显示系统以及控制显示装置的方法
公开(公告)号：US08947419B2
公开(公告)日：2015-02-03
申请号：US14183858
申请日：2014-02-19
申请人： Sharp Kabushiki Kaisha
发明人： Toshihiro Yanagi , Takuji Miyamoto , Atsuhito Murai
IPC分类号： G06F3/038 , G09G3/36 , G09G5/18
CPC分类号： G09G5/18 , G09G3/3611 , G09G2310/0283 , G09G2310/08 , G09G2340/0435
摘要： In one embodiment of the present application, a display controller is capable of changing a refresh rate, indicative of how often a screen displayed on a display device having a plurality of pixels is switched, between a low refresh rate of 40 Hz and a normal refresh rate of 60 Hz and generates (i) a dot clock (reference clock) serving as a timing signal indicative of a timing of operation in the display device, (ii) video data indicative of an image to be displayed on the screen, (iii) Hsync for defining a horizontal period of a display on the screen, and (vi) Vsync for defining a vertical period of the display on the screen, so as to supply the dot clock, the video data, Hsync, and Vsync to the display device, wherein the display controller includes a dot clock generation circuit for generating the reference clock whose frequency is constant without depending on a change of the refresh rate. This makes it possible to provide the display controller which can suppress occurrence of noise also in switching the refresh rate and which does not allow any screen derangement which is caused by the noise.
摘要翻译：在本申请的一个实施例中，显示控制器能够改变在40Hz的低刷新率和正常刷新之间指示在具有多个像素的显示设备上显示的屏幕的频率的刷新率速率为60Hz，并产生（i）用作指示显示装置中的操作定时的定时信号的点时钟（参考时钟），（ii）指示要在屏幕上显示的图像的视频数据（iii ）Hsync，用于定义屏幕上的显示的水平周期，以及（vi）Vsync，用于定义屏幕上的显示的垂直周期，以便将点时钟，视频数据，Hsync和Vsync提供给显示器装置，其中所述显示控制器包括点时钟产生电路，用于产生频率恒定的参考时钟，而不依赖于所述刷新率的改变。这使得可以在切换刷新率的同时提供能够抑制噪声发生的显示控制器，并且不允许由噪声引起的任何屏幕紊乱。

2. 发明授权

US09293594B2 Circuit board and display device 有权
标题翻译：电路板和显示设备
公开(公告)号：US09293594B2
公开(公告)日：2016-03-22
申请号：US14215338
申请日：2014-03-17
申请人： Sharp Kabushiki Kaisha
发明人： Jun Nishimura , Hideki Kitagawa , Atsuhito Murai , Hajime Imai , Shinya Tanaka , Mitsunori Imade , Tetsuo Kikuchi , Junya Shimada , Kazunori Morimoto
IPC分类号： H01L31/00 , H01L29/786 , G02F1/1333 , H01L27/12 , H01L27/02 , G02F1/1362 , G06F3/041
CPC分类号： H01L29/78663 , G02F1/13338 , G02F1/13624 , G06F3/0412 , H01L27/0207 , H01L27/0705 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L29/78633 , H01L29/7869
摘要： A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.
摘要翻译：氧化物TFT元件（3）的源极和漏极电极层（3s / 3d）由第一导电层形成。氧化物TFT元件（3）的栅极（3g）和a-Si TFT元件（5）的栅电极（5g）由单个导电层即第二导电层形成。 a-Si TFT元件（5）的源极和漏极电极层（5s / 5d）由第三导电层形成。第三导电层形成在第二导电层上方的厚度方向上，其中每个导电层堆叠在绝缘基板（2）上。此外，第一导电层在厚度方向上形成在第二导电层的下方。因此，可以提供可以使形成在绝缘基板上的晶体管元件的集成度提高的电路板。

3. 发明申请

US20140168199A1 DISPLAY CONTROLLER, DISPLAY DEVICE, DISPLAY SYSTEM, AND METHOD FOR CONTROLLING DISPLAY DEVICE 有权
标题翻译：显示控制器，显示装置，显示系统和用于控制显示装置的方法
公开(公告)号：US20140168199A1
公开(公告)日：2014-06-19
申请号：US14183858
申请日：2014-02-19
申请人： Sharp Kabushiki Kaisha
发明人： Toshihiro Yanagi , Takuji Miyamoto , Atsuhito Murai
IPC分类号： G09G5/18
CPC分类号： G09G5/18 , G09G3/3611 , G09G2310/0283 , G09G2310/08 , G09G2340/0435
摘要： In one embodiment of the present application, a display controller is capable of changing a refresh rate, indicative of how often a screen displayed on a display device having a plurality of pixels is switched, between a low refresh rate of 40 Hz and a normal refresh rate of 60 Hz and generates (i) a dot clock (reference clock) serving as a timing signal indicative of a timing of operation in the display device, (ii) video data indicative of an image to be displayed on the screen, (iii) Hsync for defining a horizontal period of a display on the screen, and (vi) Vsync for defining a vertical period of the display on the screen, so as to supply the dot clock, the video data, Hsync, and Vsync to the display device, wherein the display controller includes a dot clock generation circuit for generating the reference clock whose frequency is constant without depending on a change of the refresh rate. This makes it possible to provide the display controller which can suppress occurrence of noise also in switching the refresh rate and which does not allow any screen derangement which is caused by the noise.
摘要翻译：在本申请的一个实施例中，显示控制器能够改变在40Hz的低刷新率和正常刷新之间指示在具有多个像素的显示设备上显示的屏幕的频率的刷新率速率为60Hz，并产生（i）用作指示显示装置中的操作定时的定时信号的点时钟（参考时钟），（ii）指示要在屏幕上显示的图像的视频数据（iii ）Hsync，用于定义屏幕上的显示的水平周期，以及（vi）Vsync，用于定义屏幕上的显示的垂直周期，以便将点时钟，视频数据，Hsync和Vsync提供给显示器装置，其中所述显示控制器包括点时钟产生电路，用于产生频率恒定的参考时钟，而不依赖于所述刷新率的改变。这使得可以在切换刷新率的同时提供能够抑制噪声发生的显示控制器，并且不允许由噪声引起的任何屏幕紊乱。

4. 发明授权

US09336738B2 Display controller configured to maintain a stable pixel writing period and a gate slope period when a refresh rate is changed, display device, and control method for controlling display system and display device 有权
标题翻译：显示控制器被配置为当刷新率改变时保持稳定的像素写入周期和栅极斜率周期，显示装置和用于控制显示系统和显示装置的控制方法
公开(公告)号：US09336738B2
公开(公告)日：2016-05-10
申请号：US14518553
申请日：2014-10-20
申请人： Sharp Kabushiki Kaisha
发明人： Toshihiro Yanagi , Takuji Miyamoto , Atsuhito Murai
IPC分类号： G06F3/038 , G09G5/00 , G09G3/36
CPC分类号： G09G3/3677 , G09G5/008 , G09G2310/062 , G09G2310/08 , G09G2370/08
摘要： In one or more example embodiments, a display controller includes a stable pixel writing period in one horizontal period in a display device, the stable pixel writing period being a period during which a voltage outputted from a gate driver is at a high level. The display controller also includes a first stable pixel writing period determination circuit which determines, by using a reference signal independent from the frame rate in the display device, the stable pixel writing period during which the voltage is at the high level. Thus, the display controller can be provided in which, regardless of whether and how the frame rate is changed, the stable pixel writing period can be of a target length.
摘要翻译：在一个或多个示例性实施例中，显示控制器在显示设备中的一个水平周期中包括稳定的像素写入周期，稳定的像素写入周期是从栅极驱动器输出的电压处于高电平的时段。显示控制器还包括第一稳定像素写入周期确定电路，其通过使用独立于显示装置中的帧速率的参考信号来确定电压处于高电平的稳定像素写入周期。因此，可以提供显示控制器，其中，无论帧速率是否改变和如何改变，稳定的像素写入周期可以是目标长度。

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