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1. 发明申请

US20090214026A1 METHOD AND APPARATUS FOR OPTIMIZING ADVANCED ENCRYPTION STANDARD (AES) ENCRYPTION AND DECRYPTION IN PARALLEL MODES OF OPERATION 有权
标题翻译：用于优化并行运行模式的高级加密标准（AES）加密和分解的方法和装置
公开(公告)号：US20090214026A1
公开(公告)日：2009-08-27
申请号：US12038071
申请日：2008-02-27
申请人： Shay Gueron , Amit Gradstein , Zeev Sperber
发明人： Shay Gueron , Amit Gradstein , Zeev Sperber
IPC分类号： H04L9/06
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
摘要翻译：在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。可以通过在每个周期中调度AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。

2. 发明申请

US20140006755A1 VECTOR MULTIPLICATION WITH ACCUMULATION IN LARGE REGISTER SPACE 审中-公开
标题翻译：在大型寄存器空间中积累的矢量多项式
公开(公告)号：US20140006755A1
公开(公告)日：2014-01-02
申请号：US13538523
申请日：2012-06-29
申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
发明人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F7/52 , G06F9/30018 , G06F9/30036
摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
摘要翻译：描述了具有指令执行流水线的装置，其具有支持向量乘法加法指令的向量功能单元。向量乘以相乘指令乘以两个向量的各个K位元素，并将其各自产物的一部分与X位累加器中的另一个相应输入操作数进行累加，其中X大于K.

3. 发明授权

US08600049B2 Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation 有权
标题翻译：用于在并行运行模式下优化先进加密标准（AES）加密和解密的方法和装置
公开(公告)号：US08600049B2
公开(公告)日：2013-12-03
申请号：US13506701
申请日：2012-05-10
申请人： Shay Gueron , Amit Gradstein , Zeev Sperber
发明人： Shay Gueron , Amit Gradstein , Zeev Sperber
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
摘要翻译：在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。可以通过在每个周期中调度AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。

4. 发明申请

US20120224687A1 Method and apparatus for optimizing Advanced Encryption Standard (AES) encryption and decryption in parallel modes of operation 有权
标题翻译：用于在并行运行模式下优化高级加密标准（AES）加密和解密的方法和装置
公开(公告)号：US20120224687A1
公开(公告)日：2012-09-06
申请号：US13506701
申请日：2012-05-10
申请人： Shay Gueron , Amit Gradstein , Zeev Sperber
发明人： Shay Gueron , Amit Gradstein , Zeev Sperber
IPC分类号： G06F21/24
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
摘要翻译：在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。可以通过在每个周期中调度AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。

5. 发明授权

US10095516B2 Vector multiplication with accumulation in large register space 有权
公开(公告)号：US10095516B2
公开(公告)日：2018-10-09
申请号：US13538523
申请日：2012-06-29
申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
发明人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
IPC分类号： G06F9/30 , G06F7/52 , G06F9/38
摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.

6. 发明授权

US08194854B2 Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation 有权
标题翻译：用于在并行运行模式下优化先进加密标准（AES）加密和解密的方法和装置
公开(公告)号：US08194854B2
公开(公告)日：2012-06-05
申请号：US12038071
申请日：2008-02-27
申请人： Shay Gueron , Amit Gradstein , Zeev Sperber
发明人： Shay Gueron , Amit Gradstein , Zeev Sperber
IPC分类号： H04L9/06 , H04L9/00 , H04L9/30 , H04L9/28 , H03K19/173 , H04K1/04
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
摘要翻译：在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。可以通过在每个周期中调度AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。

7. 发明申请

US20090220071A1 COMBINING INSTRUCTIONS INCLUDING AN INSTRUCTION THAT PERFORMS A SEQUENCE OF TRANSFORMATIONS TO ISOLATE ONE TRANSFORMATION 有权
标题翻译：组合指令，包括执行转换序列以隔离一次转换的指令
公开(公告)号：US20090220071A1
公开(公告)日：2009-09-03
申请号：US12040214
申请日：2008-02-29
申请人： Shay Gueron , Zeev Sperber
发明人： Shay Gueron , Zeev Sperber
IPC分类号： H04L9/28
CPC分类号： H04L9/0681 , G06F9/30007 , G06F21/75 , G06F2221/2107 , G09C1/00 , H04L9/0631 , H04L2209/125 , H04L2209/24
摘要： The Advanced Encryption Standard (AES) is a symmetric block cipher that can encrypt and decrypt information. Encryption (cipher) performs a series of transformations (Shift Rows, Substitute Bytes, Mix Columns) using the secret key (cipher key) to transforms intelligible data referred to as “plaintext” into an unintelligible form referred to as “cipher text”. The transformations (Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) in the inverse cipher (decryption) are the inverse of the transformations in the cipher. Encryption and decryption is performed efficiently through the use of instructions that perform the series of transformations. Combinations of these instructions allow the isolation of the transformations (Shift Rows, Substitute Bytes, Mix Columns, Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) to be obtained.
摘要翻译：高级加密标准（AES）是可以加密和解密信息的对称块密码。加密（密码）使用秘密密钥（密码密钥）执行一系列转换（Shift Rows，Substitute Bytes，Mix Columns），将被称为“明文”的可理解数据转换成称为“密文”的无法理解的形式。反密码（解密）中的变换（逆位排，逆替换字节，反混合列）是密码中的变换的逆。通过使用执行一系列转换的指令来有效地执行加密和解密。这些指令的组合允许要获得的转换的隔离（Shift Rows，Substitution Bytes，Mix Columns，Inverse Shift Rows，Inverse Substitute Bytes，Inverse Mix Columns）。

8. 发明授权

US08879725B2 Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation 有权
标题翻译：组合指令，包括执行转换序列以隔离一个转换的指令
公开(公告)号：US08879725B2
公开(公告)日：2014-11-04
申请号：US12040214
申请日：2008-02-29
申请人： Shay Gueron , Zeev Sperber
发明人： Shay Gueron , Zeev Sperber
IPC分类号： H04K1/00 , H04L9/32 , H04L9/06 , G06F21/75
CPC分类号： H04L9/0681 , G06F9/30007 , G06F21/75 , G06F2221/2107 , G09C1/00 , H04L9/0631 , H04L2209/125 , H04L2209/24
摘要： The Advanced Encryption Standard (AES) is a symmetric block cipher that can encrypt and decrypt information. Encryption (cipher) performs a series of transformations (Shift Rows, Substitute Bytes, Mix Columns) using the secret key (cipher key) to transforms intelligible data referred to as “plaintext” into an unintelligible form referred to as “cipher text”. The transformations (Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) in the inverse cipher (decryption) are the inverse of the transformations in the cipher. Encryption and decryption is performed efficiently through the use of instructions that perform the series of transformations. Combinations of these instructions allow the isolation of the transformations (Shift Rows, Substitute Bytes, Mix Columns, Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) to be obtained.
摘要翻译：高级加密标准（AES）是可以加密和解密信息的对称块密码。加密（密码）使用秘密密钥（密码密钥）执行一系列转换（Shift Rows，Substitute Bytes，Mix Columns），将被称为“明文”的可理解数据转换成称为“密文”的无法理解的形式。反密码（解密）中的变换（逆位排，逆替换字节，反混合列）是密码中的变换的逆。通过使用执行一系列转换的指令来有效地执行加密和解密。这些指令的组合允许要获得的转换的隔离（Shift Rows，Substitution Bytes，Mix Columns，Inverse Shift Rows，Inverse Substitute Bytes，Inverse Mix Columns）。

9. 发明申请

US20200348361A1 SYSTEMS AND METHODS FOR INTELLECTUAL PROPERTY-SECURED, REMOTE DEBUGGING 审中-公开
公开(公告)号：US20200348361A1
公开(公告)日：2020-11-05
申请号：US16403296
申请日：2019-05-03
申请人： Tsvika Kurts , Boris Dolgunov , Vladislav Mladentsev , Ittai Anati , Elias Khoury , Maor Kima , Eran Shlomo , Shay Gueron , William Penner
发明人： Tsvika Kurts , Boris Dolgunov , Vladislav Mladentsev , Ittai Anati , Elias Khoury , Maor Kima , Eran Shlomo , Shay Gueron , William Penner
IPC分类号： G01R31/317 , G06F11/263 , H04L9/08 , H04L9/32 , H04L9/06 , G06F16/22 , G01R31/3177
摘要： Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.

10. 发明授权

US09559848B2 Method, apparatus, and instructions for safely storing secrets in system memory 有权
标题翻译：用于在系统存储器中安全存储秘密的方法，装置和说明
公开(公告)号：US09559848B2
公开(公告)日：2017-01-31
申请号：US14467425
申请日：2014-08-25
申请人： Shay Gueron
发明人： Shay Gueron
IPC分类号： H04L9/32 , H04L9/08
CPC分类号： G06F12/1408 , G06F21/72 , G06F21/73 , G06F21/74 , G06F2212/1052 , G06F2221/2107 , H04L9/0637 , H04L9/0894 , H04L9/3226 , H04L63/083
摘要： Embodiments of an invention for method, apparatus, and instructions for safely storing secrets in system memory are disclosed. In one embodiment, a processor includes a hardware key, an instruction unit, and an encryption unit. The instruction unit is to receive an encryption instruction and a compare instruction. The encryption instruction is to have a first plaintext input value. The compare instruction is to have a second plaintext input value. The encryption unit is to, in response to the encryption instruction, encrypt the first plaintext input value using the hardware key to generate a ciphertext value, and, in response to the compare instruction, decrypt the ciphertext value using the hardware key to generate a plaintext output value and compare the plaintext output value to the second plaintext input value.
摘要翻译：公开了用于在系统存储器中安全地存储秘密的方法，装置和指令的发明的实施例。在一个实施例中，处理器包括硬件密钥，指令单元和加密单元。指令单元接收加密指令和比较指令。加密指令是具有第一个明文输入值。比较指令是具有第二个明文输入值。加密单元响应于加密指令，使用硬件密钥对第一明文输入值进行加密，以生成密文值，并且响应于比较指令，使用硬件密钥解密密文值以生成明文输出值，并将明文输出值与第二个明文输入值进行比较。

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