专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08955388B2 Mold compound compatibility test system and methods thereof 有权
标题翻译：模具复合相容性试验系统及其方法
公开(公告)号：US08955388B2
公开(公告)日：2015-02-17
申请号：US13484353
申请日：2012-05-31
申请人： Varughese Mathew , Sheila F. Chopin , Leo M. Higgins, III
发明人： Varughese Mathew , Sheila F. Chopin , Leo M. Higgins, III
IPC分类号： G01N3/08
CPC分类号： G01N19/04 , G01N3/24 , H01L22/12 , H01L2224/48227 , H01L2224/48465 , H01L2924/00
摘要： A technique for testing the compatibility of an encapsulation material and a wire bond included at an unencapsulated assembly. The technique includes immersing the assembly in an encapsulating compound extract. The assembly includes a semiconductor die and a bonding wire affixed to a metalized pad of the semiconductor die by the wire bond. After the immersing, a mechanical strength of the wire bond is determined.
摘要翻译：一种用于测试包封在未封装组件中的封装材料和引线键合的相容性的技术。该技术包括将组件浸入封装化合物提取物中。组件包括半导体管芯和通过引线接合固定到半导体管芯的金属化焊盘的接合线。浸渍后，确定线接合的机械强度。

2. 发明授权

US08836110B2 Heat spreader for use within a packaged semiconductor device 有权
标题翻译：用于封装半导体器件内的散热器
公开(公告)号：US08836110B2
公开(公告)日：2014-09-16
申请号：US13600364
申请日：2012-08-31
申请人： Sheila F. Chopin , Varughese Mathew
发明人： Sheila F. Chopin , Varughese Mathew
IPC分类号： H01L23/34 , F28F7/00 , H01L21/56
CPC分类号： H01L21/565 , H01L21/56 , H01L23/3128 , H01L23/4334 , H01L2224/48091 , H01L2924/1815 , H01L2924/00014
摘要： A packaged semiconductor device includes a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.
摘要翻译：封装的半导体器件包括封装衬底，安装在封装衬底上的集成电路（IC）裸片和安装在封装衬底上的散热器。散热器围绕IC芯片的至少一部分，并且包括具有多个开口的盖。散热器的内部包括与模具相邻的多个导热突起。

3. 发明授权

US09426884B2 System and method for lead frame package degating 有权
标题翻译：引线框封装脱胶的系统和方法
公开(公告)号：US09426884B2
公开(公告)日：2016-08-23
申请号：US13950618
申请日：2013-07-25
申请人： Sheila F. Chopin , Varughese Mathew
发明人： Sheila F. Chopin , Varughese Mathew
IPC分类号： H05K1/11 , H05K1/05 , H05K3/28 , H01L21/56 , H01L21/48 , H01L23/495 , H01L23/31 , H01L23/00
CPC分类号： H05K1/05 , H01L21/4821 , H01L21/56 , H01L23/3107 , H01L23/49541 , H01L23/49586 , H01L24/97 , H01L2924/15747 , H01L2924/1815 , H05K1/111 , H05K3/28 , Y10T29/49121 , H01L2924/00
摘要： A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. The metal sheet includes metal oxide in a select area. The pad region is substantially free of metal oxide.
摘要翻译：形成电子部件的方法包括：遮蔽引线框架以形成限定暴露区域的掩模，氧化引线框架的暴露区域，其中掩模禁止未曝光区域的氧化，并且在氧化之后从引线框架去除掩模。引线框架可以包括图案化以限定焊盘区域和引线的金属板。金属片在选择区域中包括金属氧化物。焊盘区域基本上不含金属氧化物。

4. 发明授权

US09412709B2 Semiconductor structure with sacrificial anode and passivation layer and method for forming 有权
标题翻译：具有牺牲阳极和钝化层的半导体结构及其形成方法
公开(公告)号：US09412709B2
公开(公告)日：2016-08-09
申请号：US13898949
申请日：2013-05-21
申请人： Sheila F. Chopin , Min Ding , Varughese Mathew , Scott S. Roth
发明人： Sheila F. Chopin , Min Ding , Varughese Mathew , Scott S. Roth
IPC分类号： H01L21/56 , H01L21/44 , H01L23/00 , H01L23/31
CPC分类号： H01L24/02 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0218 , H01L2224/0219 , H01L2224/03005 , H01L2224/03009 , H01L2224/03015 , H01L2224/03019 , H01L2224/034 , H01L2224/03622 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/05 , H01L2224/05565 , H01L2224/05567 , H01L2224/05624 , H01L2224/131 , H01L2224/13147 , H01L2224/32145 , H01L2224/45124 , H01L2224/45147 , H01L2224/48227 , H01L2224/48463 , H01L2224/48507 , H01L2224/48824 , H01L2224/73265 , H01L2924/01012 , H01L2924/01029 , H01L2924/0103 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/365 , H01L2924/3651 , H01L2924/014 , H01L2924/00014 , H01L2924/00
摘要： A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
摘要翻译：通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。

5. 发明申请

US20150027767A1 SYSTEM AND METHOD FOR LEAD FRAME PACKAGE DEGATING 有权
标题翻译：引导框架包装降解的系统和方法
公开(公告)号：US20150027767A1
公开(公告)日：2015-01-29
申请号：US13950618
申请日：2013-07-25
申请人： Sheila F. Chopin , Varughese Mathew
发明人： Sheila F. Chopin , Varughese Mathew
IPC分类号： H01L21/56 , H01L21/48 , H01L23/495
CPC分类号： H05K1/05 , H01L21/4821 , H01L21/56 , H01L23/3107 , H01L23/49541 , H01L23/49586 , H01L24/97 , H01L2924/15747 , H01L2924/1815 , H05K1/111 , H05K3/28 , Y10T29/49121 , H01L2924/00
摘要： A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. The metal sheet includes metal oxide in a select area. The pad region is substantially free of metal oxide.
摘要翻译：形成电子部件的方法包括：遮蔽引线框架以形成限定暴露区域的掩模，氧化引线框架的暴露区域，其中掩模禁止未曝光区域的氧化，并且在氧化之后从引线框架去除掩模。引线框架可以包括图案化以限定焊盘区域和引线的金属板。金属片在选择区域中包括金属氧化物。焊盘区域基本上不含金属氧化物。

6. 发明申请

US20140346663A1 SEMICONDUCTOR STRUCTURE WITH SACRIFICIAL ANODE AND METHOD FOR FORMING 有权
标题翻译：具有阳离子阳极的半导体结构和形成方法
公开(公告)号：US20140346663A1
公开(公告)日：2014-11-27
申请号：US13898949
申请日：2013-05-21
申请人： Sheila F. Chopin , Min Ding , Varughese Mathew , Scott S. Roth
发明人： Sheila F. Chopin , Min Ding , Varughese Mathew , Scott S. Roth
IPC分类号： H01L23/00
CPC分类号： H01L24/02 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0218 , H01L2224/0219 , H01L2224/03005 , H01L2224/03009 , H01L2224/03015 , H01L2224/03019 , H01L2224/034 , H01L2224/03622 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/05 , H01L2224/05565 , H01L2224/05567 , H01L2224/05624 , H01L2224/131 , H01L2224/13147 , H01L2224/32145 , H01L2224/45124 , H01L2224/45147 , H01L2224/48227 , H01L2224/48463 , H01L2224/48507 , H01L2224/48824 , H01L2224/73265 , H01L2924/01012 , H01L2924/01029 , H01L2924/0103 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/365 , H01L2924/3651 , H01L2924/014 , H01L2924/00014 , H01L2924/00
摘要： A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
摘要翻译：通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。

7. 发明申请

US20140061894A1 HEAT SPREADER FOR USE WITHIN A PACKAGED SEMICONDUCTOR DEVICE 有权
标题翻译：在包装半导体器件中使用的热扩散器
公开(公告)号：US20140061894A1
公开(公告)日：2014-03-06
申请号：US13600364
申请日：2012-08-31
申请人： Sheila F. Chopin , Varughese Mathew
发明人： Sheila F. Chopin , Varughese Mathew
IPC分类号： H01L23/34 , F28F7/00 , H01L21/56
CPC分类号： H01L21/565 , H01L21/56 , H01L23/3128 , H01L23/4334 , H01L2224/48091 , H01L2924/1815 , H01L2924/00014
摘要： A packaged semiconductor device, comprising a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.
摘要翻译：一种封装半导体器件，包括封装衬底，安装在封装衬底上的集成电路（IC）裸片和安装在封装衬底上的散热器。散热器围绕IC芯片的至少一部分，并且包括具有多个开口的盖。散热器的内部包括与模具相邻的多个导热突起。

8. 发明申请

US20130319129A1 MOLD COMPOUND COMPATIBILITY TEST SYSTEM AND METHODS THEREOF 有权
标题翻译：模具化合物相容性测试系统及其方法
公开(公告)号：US20130319129A1
公开(公告)日：2013-12-05
申请号：US13484353
申请日：2012-05-31
申请人： Varughese Mathew , Sheila F. Chopin , Leo M. Higgins, III
发明人： Varughese Mathew , Sheila F. Chopin , Leo M. Higgins, III
IPC分类号： G01N3/08 , H01L21/66 , H01L21/56
CPC分类号： G01N19/04 , G01N3/24 , H01L22/12 , H01L2224/48227 , H01L2224/48465 , H01L2924/00
摘要： A technique for testing the compatibility of an encapsulation material and a wire bond included at an unencapsulated assembly. The technique includes immersing the assembly in an encapsulating compound extract. The assembly includes a semiconductor die and a bonding wire affixed to a metalized pad of the semiconductor die by the wire bond. After the immersing, a mechanical strength of the wire bond is determined.
摘要翻译：一种用于测试包封在未封装组件中的封装材料和引线键合的相容性的技术。该技术包括将组件浸入封装化合物提取物中。组件包括半导体管芯和通过引线接合固定到半导体管芯的金属化焊盘的接合线。浸渍后，确定线接合的机械强度。

9. 发明授权

US09117756B2 Encapsulant with corrosion inhibitor 有权
标题翻译：具有缓蚀剂的密封剂
公开(公告)号：US09117756B2
公开(公告)日：2015-08-25
申请号：US13361171
申请日：2012-01-30
申请人： Varughese Mathew
发明人： Varughese Mathew
IPC分类号： H01L23/29 , H01L23/28 , H01L23/00 , C08K5/09
CPC分类号： H01L23/293 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/45124 , H01L2224/48463 , H01L2924/181 , H01L2924/00
摘要： A packaged electronic device including an electronic device, a conductive structure, and an encapsulant. The encapsulant has chlorides and a negatively-charged corrosion inhibitor for preventing corrosion of the conductive structure.
摘要翻译：包括电子器件，导电结构和密封剂的封装电子器件。密封剂具有氯化物和带负电荷的腐蚀抑制剂，用于防止导电结构的腐蚀。

10. 发明授权

US07932175B2 Method to form a via 有权
标题翻译：形成通孔的方法
公开(公告)号：US07932175B2
公开(公告)日：2011-04-26
申请号：US11807745
申请日：2007-05-29
申请人： Ritwik Chatterjee , Eddie Acosta , Sam S. Garcia , Varughese Mathew
发明人： Ritwik Chatterjee , Eddie Acosta , Sam S. Garcia , Varughese Mathew
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898
摘要： A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.
摘要翻译：一种用于形成通孔的方法，包括（a）提供包括设置在半导体衬底（203）上的掩模（210）的结构，其中所述结构具有限定在其中的开口（215），所述开口延伸穿过所述掩模并进入所述衬底，并且其中所述掩模包括第一导电层; （b）沉积第二导电层（219），使得所述第二导电层与所述第一导电层电接触，所述第二导电层具有在所述开口的表面上延伸的第一部分，所述第二部分延伸在面罩的与开口相邻的一部分上方; （c）去除第二导电层的第二部分; 和（d）在第二导电层的第一部分上沉积第一金属（221）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式