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1. 发明申请

US20120317125A1 METHOD AND APPARATUS FOR IDENTIFIER RETRIEVAL 审中-公开
标题翻译：识别器检索的方法和装置
公开(公告)号：US20120317125A1
公开(公告)日：2012-12-13
申请号：US13590479
申请日：2012-08-21
申请人： Sheng Hua Bao , HongLei Guo , Zhong Su , Jian Yao , Li Zhang , Shuo Zhang , Hui Jia Zhu
发明人： Sheng Hua Bao , HongLei Guo , Zhong Su , Jian Yao , Li Zhang , Shuo Zhang , Hui Jia Zhu
IPC分类号： G06F17/30
CPC分类号： G06F16/367 , G06F16/20
摘要： A method for identifier retrieval. The method can include the steps of: extracting candidate identifiers from a data source according to a source identifier; obtaining a profile of the source identifier and profiles of the candidate identifiers from the data source; and selecting a target identifier associated with the source identifier from the candidate identifiers according to the profile of the source identifier and the profiles of the candidate identifiers. The method may efficiently, accurately and rapidly find a target identifier associated with a source identifier.
摘要翻译：一种用于标识符检索的方法。该方法可以包括以下步骤：根据源标识符从数据源中提取候选标识符; 从数据源获取候选标识符的源标识符和简档的简档; 以及根据源标识符的简档和候选标识符的简档，从候选标识符中选择与源标识符相关联的目标标识符。该方法可以有效，准确和快速地找到与源标识符相关联的目标标识符。

2. 发明申请

US20120296932A1 METHOD AND APPARATUS FOR IDENTIFIER RETRIEVAL 审中-公开
公开(公告)号：US20120296932A1
公开(公告)日：2012-11-22
申请号：US13471515
申请日：2012-05-15
申请人： Sheng Hua Bao , HongLei Guo , Zhong Su , Jian Yao , Li Zhang , Shuo Zhang , Hui Jia Zhu
发明人： Sheng Hua Bao , HongLei Guo , Zhong Su , Jian Yao , Li Zhang , Shuo Zhang , Hui Jia Zhu
IPC分类号： G06F17/30
CPC分类号： G06F16/367 , G06F16/20
摘要： A method for identifier retrieval. The method can include the steps of: extracting candidate identifiers from a data source according to a source identifier; obtaining a profile of the source identifier and profiles of the candidate identifiers from the data source; and selecting a target identifier associated with the source identifier from the candidate identifiers according to the profile of the source identifier and the profiles of the candidate identifiers. The method may efficiently, accurately and rapidly find a target identifier associated with a source identifier.

3. 发明申请

US20130041479A1 AUTOMATED CONTROL SYSTEM AND SUPERVISOR SCHEDULER USABLE WITH SAME 审中-公开
标题翻译：自动控制系统和可与其同时使用的监控调度器
公开(公告)号：US20130041479A1
公开(公告)日：2013-02-14
申请号：US13225395
申请日：2011-09-02
申请人： Shuo Zhang , Chandra Sekhar Inturi , Christopher LaBello , Alan M. Ganz
发明人： Shuo Zhang , Chandra Sekhar Inturi , Christopher LaBello , Alan M. Ganz
IPC分类号： G05B15/02
CPC分类号： G05B19/056 , G05B2219/31334 , Y02P90/16 , Y02P90/185
摘要： A computerized method of offering a comprehensive control system for varied kinds of manufactures, including: providing a computer graphical user interface having the static model of hardware systems, information and status of the control system and context of the automation procedure commands; providing a hardware database containing 1) port database including all ports of a controller connecting to devices, 2) a device database including information, operation methods, events of all devices connected to the controller, 3) a system database including information and configuration of all systems that controller controls; providing a dictionary containing word pairs that define operations and status of every device; providing a background worker responsible for refreshing data from port database. Computer systems configured to perform the method.
摘要翻译：提供一种用于各种制造商的综合控制系统的计算机化方法，包括：提供具有硬件系统的静态模型，控制系统的信息和状态以及自动化过程命令的上下文的计算机图形用户界面; 提供硬件数据库，其中包含1）端口数据库，包括连接到设备的控制器的所有端口; 2）设备数据库，包括与控制器连接的所有设备的信息，操作方法，事件; 3）系统数据库，包括所有信息和配置控制器控制的系统; 提供一个包含用于定义每个设备的操作和状态的字对的字典; 提供负责从端口数据库刷新数据的后台工作人员。配置为执行该方法的计算机系统。

4. 发明申请

US20060288322A1 Incremental geotopological layout for integrated circuit design 失效
公开(公告)号：US20060288322A1
公开(公告)日：2006-12-21
申请号：US11450142
申请日：2006-06-09
申请人： Shuo Zhang , Yongbo Jia
发明人： Shuo Zhang , Yongbo Jia
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures layout validity. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach enables an IC designer to modify a routed layout for various optimization targets, while maintaining the exact routing paths of critical nets that are not modifiable. Geotopological layout optimization according to the present invention can be performed on an entire layout, or it can be performed incrementally on one or more sub-layouts of a design.

5. 发明申请

US20060064654A1 Routed layout optimization with geotopological layout encoding for integrated circuit designs 失效
公开(公告)号：US20060064654A1
公开(公告)日：2006-03-23
申请号：US10946918
申请日：2004-09-21
申请人： Shuo Zhang , Yongbo Jia
发明人： Shuo Zhang , Yongbo Jia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5077
摘要： The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some by their respective wiring topology at the same time. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures the validity thereof. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach advantageously enables an IC designer to modify a routed layout for various optimization targets, while advantageously maintaining the exact routing paths of critical nets that are not modifiable.

6. 外观设计

USD906722S1 Tube squeezer 有权
公开(公告)号：USD906722S1
公开(公告)日：2021-01-05
申请号：US29712781
申请日：2019-11-12
申请人： Shuo Zhang
设计人： Shuo Zhang

7. 发明申请

US20120005295A1 Method and Device for Mail Processing 审中-公开
标题翻译：邮件处理方法和设备
公开(公告)号：US20120005295A1
公开(公告)日：2012-01-05
申请号：US13256808
申请日：2010-03-02
申请人： Dianzhi Wang , Shuo Zhang , Shengdo Li
发明人： Dianzhi Wang , Shuo Zhang , Shengdo Li
IPC分类号： G06F15/16
CPC分类号： G06Q10/00 , H04L29/06 , H04L51/00
摘要： A method and device for mail processing are provided by embodiments of the present invention. The method comprises: acquiring a first description information of a first mail, wherein the first description information comprises a first mail content and a first display description information of the first mail content; acquiring a first format of the first mail and a second format of a second mail; converting the first mail content in the first format into a second mail content in the second format; converting the first display description information in the first format into a second display description information in the second format; obtaining the second mail according to a second description information comprising the second mail content and the second display description information, wherein the display of the second mail content within the second mail according to the second display description information is consistent with the display of the first mail content within the first mail according to the first display description information. The implementation of the technical solutions provided by the embodiments of the invention enables a user receiving the second mail to see the mail information comparatively consistent with the information intended to be expressed by the first mail.
摘要翻译：用于邮件处理的方法和装置由本发明的实施例提供。该方法包括：获得第一邮件的第一描述信息，其中第一描述信息包括第一邮件内容和第一邮件内容的第一显示描述信息; 获取第一邮件的第一格式和第二邮件的第二格式; 将第一格式的第一邮件内容转换成第二格式的第二邮件内容; 将第一格式的第一显示描述信息转换为第二格式的第二显示描述信息; 根据包括第二邮件内容和第二显示描述信息的第二描述信息来获取第二邮件，其中根据第二显示描述信息显示第二邮件内的第二邮件内容与第一邮件的显示一致根据第一显示描述信息在第一邮件内的内容。由本发明的实施例提供的技术方案的实现使得接收第二邮件的用户能够看到与预期由第一邮件表达的信息相比一致的邮件信息。

8. 发明授权

US07526746B2 Incremental geotopological layout for integrated circuit design 失效
标题翻译：集成电路设计的增量式地理布局
公开(公告)号：US07526746B2
公开(公告)日：2009-04-28
申请号：US11450142
申请日：2006-06-09
申请人： Shuo Zhang , Yongbo Jia
发明人： Shuo Zhang , Yongbo Jia
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures layout validity. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach enables an IC designer to modify a routed layout for various optimization targets, while maintaining the exact routing paths of critical nets that are not modifiable. Geotopological layout optimization according to the present invention can be performed on an entire layout, or it can be performed incrementally on one or more sub-layouts of a design.
摘要翻译：提供详细路由后物理设计阶段改进的集成电路（IC）设计优化。采用地理布局表示，其中一些网络由它们确定的几何布线路径和其他网络通过它们各自的布线拓扑来表示。在IC设计流程中，具有几何布线路径的路由布局被转换为地理布局。然后根据地理布局进行所有布局修改。嵌入式设计规则检查器确保布局有效性。最后，相应地重新生成新的几何布局，包括针对目标优化的所有布局更改。这种地理学方法使IC设计人员可以修改各种优化目标的路由布局，同时保持不可修改的关键网络的确切路由路径。根据本发明的地理布局优化可以在整个布局上执行，或者可以在设计的一个或多个子布局上递增地执行。

9. 发明授权

US07380231B2 Wire spreading through geotopological layout 失效
标题翻译：电线通过地理布局布置
公开(公告)号：US07380231B2
公开(公告)日：2008-05-27
申请号：US11146485
申请日：2005-06-06
申请人： Shuo Zhang , Fangyi Luo
发明人： Shuo Zhang , Fangyi Luo
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The present invention provides a layout yield improvement tool that performs wire spreading to optimize integrated circuit (IC) designs in the physical design stage after detail routing. Preferably, the wire spreading is performed on a geotopological layout. Each modifiable wire thereof is processed to generate a geometric bottom-up shape (BUS) and a top-down shape (TDS). The BUS and TDS are merged to form a final geometrical Middle Shape (MS). Each point in the MS has a position is averaged from the positions of the two correlated points in the BUS and TDS. Unnecessary short jogs are removed from the MS of each wire. A final layout is generated by combining all of the final geometric shapes of each wire segments. As such, the wire-to-wire spacing is increased to more than the minimum spacing requirement without causing any design rule violations.
摘要翻译：本发明提供了一种布局产量改进工具，其在细节布线之后，在物理设计阶段执行线扩展以优化集成电路（IC）设计。优选地，布线在地理布局上进行。每个可修改的线被处理以产生几何自下而上形状（BUS）和自顶向下形状（TDS）。 BUS和TDS合并形成最终的几何中间形状（MS）。 MS中的每个点具有从BUS和TDS中的两个相关点的位置进行平均的位置。从每根电线的MS上移除不需要的短点动作。通过组合每个线段的所有最终几何形状来生成最终布局。因此，线对线间距增加到超过最小间距要求，而不会导致任何设计规则违规。

10. 发明授权

US07131095B2 Routed layout optimization with geotopological layout encoding for integrated circuit designs 失效
标题翻译：路由布局优化与集成电路设计的地理布局编码
公开(公告)号：US07131095B2
公开(公告)日：2006-10-31
申请号：US10946918
申请日：2004-09-21
申请人： Shuo Zhang , Yongbo Jia
发明人： Shuo Zhang , Yongbo Jia
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some by their respective wiring topology at the same time. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures the validity thereof. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach advantageously enables an IC designer to modify a routed layout for various optimization targets, while advantageously maintaining the exact routing paths of critical nets that are not modifiable.
摘要翻译：本发明提供了一种在细节路由后物理设计阶段优化集成电路（IC）设计的新方法。一个关键要素是一种新颖的混合布局表示，被称为地理布局，其中一些网由其确定的几何布线路径表示，一些网由其各自的布线拓扑同时表示。在IC设计流程中，具有几何布线路径的路由布局被转换为地理布局。然后根据地理布局进行所有布局修改。嵌入式设计规则检查器确保其有效性。最后，相应地重新生成新的几何布局，包括针对目标优化的所有布局更改。这种地理学方法有利地使得IC设计者可以修改用于各种优化目标的路由布局，同时有利地维护不可修改的关键网络的确切路由路径。

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