专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09171618B2 Semiconductor integrated circuit and processor 有权
标题翻译：半导体集成电路和处理器
公开(公告)号：US09171618B2
公开(公告)日：2015-10-27
申请号：US13556431
申请日：2012-07-24
申请人： Shinobu Fujita , Keiko Abe
发明人： Shinobu Fujita , Keiko Abe
IPC分类号： G11C11/00 , G11C14/00
CPC分类号： G11C14/0054 , G11C11/16 , G11C14/0081
摘要： In one embodiment, there is provided a semiconductor integrated circuit that includes: a first inverter; a second inverter; a first transistor, wherein one end of the first transistor is connected to a first bit line and the other end of the first transistor is connected to a first input terminal of the first inverter; a first element group including second transistors, wherein one end of the first element group is connected to a first output terminal of the first inverter and the other end of the first element group is connected to a second bit line; and a second element group including third transistors and a magnetoresistive element whose magnetic resistance is varied. The second element group is disposed between the second output terminal of the second inverter and a first terminal or disposed between the first transistor and the first terminal.
摘要翻译：在一个实施例中，提供了一种半导体集成电路，其包括：第一反相器; 第二个逆变器; 第一晶体管，其中第一晶体管的一端连接到第一位线，第一晶体管的另一端连接到第一反相器的第一输入端; 包括第二晶体管的第一元件组，其中第一元件组的一端连接到第一反相器的第一输出端子，第一元件组的另一端连接到第二位线; 以及包括第三晶体管和磁阻变化的磁阻元件的第二元件组。第二元件组设置在第二反相器的第二输出端子与第一端子之间或者设置在第一晶体管和第一端子之间。

2. 发明授权

US09026830B2 Information processing apparatus 有权
标题翻译：信息处理装置
公开(公告)号：US09026830B2
公开(公告)日：2015-05-05
申请号：US13421090
申请日：2012-03-15
申请人： Keiko Abe , Shinobu Fujita
发明人： Keiko Abe , Shinobu Fujita
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/13 , Y02D10/14
摘要： One embodiment provides an information processing apparatus including a processor; memory blocks; an internal voltage generator connected to the memory blocks; an input/output circuit connected to the memory blocks; switches each installed corresponding to the internal voltage generator, the input/output circuit, and the memory blocks, and configured to switch ON/OFF of the connection with a power source; a data register configured to store a data set that controls the ON/OFF of the switches; and a data management circuit configured to set the data set in the data register, wherein when a clock signal input to the processor is turned to OFF, the data management circuit generates a first type of the data set, which switches ON the switch connected to the internal voltage generator and switches OFF the switches connected to the memory blocks, and sets the first type of the data set in the data register.
摘要翻译：一个实施例提供一种包括处理器的信息处理设备; 记忆块连接到存储块的内部电压发生器; 连接到存储器块的输入/输出电路; 对应于内部电压发生器，输入/输出电路和存储器块的每个安装开关，并被配置为用电源来切换连接的ON / OFF; 数据寄存器，被配置为存储控制开关的ON / OFF的数据组; 以及数据管理电路，被配置为将数据集设置在数据寄存器中，其中当输入到处理器的时钟信号变为OFF时，数据管理电路产生第一类型的数据组，其将接通的开关内部电压发生器和断开连接到存储器块的开关，并将数据集的第一种类型设置在数据寄存器中。

3. 发明授权

US08742810B2 PLL (phase-locked loop) 失效
标题翻译： PLL（锁相环）
公开(公告)号：US08742810B2
公开(公告)日：2014-06-03
申请号：US13461101
申请日：2012-05-01
申请人： Hiroki Noguchi , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
发明人： Hiroki Noguchi , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
IPC分类号： H03L7/06
CPC分类号： H03L7/14 , H03L2207/18
摘要： One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.
摘要翻译：一个实施例提供了一种锁相环（PLL），其中定序器控制环路滤波器，使得当指示关闭PLL的电源的信号被输入时，或者当指示接通 PLL的电源被输入到其中，环路滤波器中的第一电阻改变装置的电阻值是第一电阻值，并且在PLL稳定之后，第一电阻改变装置的电阻值是第二电阻值电阻值高于第一电阻值。

4. 发明授权

US08497732B2 Three-dimensional semiconductor integrated circuit 有权
标题翻译：三维半导体集成电路
公开(公告)号：US08497732B2
公开(公告)日：2013-07-30
申请号：US13223898
申请日：2011-09-01
申请人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
发明人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
IPC分类号： H01L25/00
CPC分类号： H03K19/20 , G11C5/02 , H01L23/642 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/49113 , H01L2225/06513 , H01L2225/06527 , H01L2225/06531 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01033 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19104 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： According to one embodiment, a three-dimensional semiconductor integrated circuit includes first, second and third chips which are stacked, and a common conductor which connects the first, second and third chips from one another. The first chip includes a first multi-leveling circuit, the second chip includes a second multi-leveling circuit, and the third chip includes a decoding circuit. The first multi-leveling circuit includes a first inverter to which binary first data is input and which outputs one of first and second potentials and a first capacitor which is connected between an output terminal of the first inverter and the common conductor. The second multi-leveling circuit includes a second inverter to which binary second data is input and which outputs one of third and fourth potentials and a second capacitor which is connected between an output terminal of the second inverter and the common conductor.
摘要翻译：根据一个实施例，三维半导体集成电路包括堆叠的第一，第二和第三芯片，以及将第一，第二和第三芯片彼此连接的公共导体。第一芯片包括第一多电平电路，第二芯片包括第二多电平电路，第三芯片包括解码电路。第一多电平电路包括输入二进制第一数据并输出第一和第二电位之一的第一反相器和连接在第一反相器的输出端和公共导体之间的第一电容器。第二多电平电路包括输入二进制第二数据并输出第三和第四电位之一的第二反相器和连接在第二反相器的输出端和公共导体之间的第二电容器。

5. 发明授权

US08331130B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08331130B2
公开(公告)日：2012-12-11
申请号：US12880758
申请日：2010-09-13
申请人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
发明人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/75 , H03K19/17728 , H03K19/1776
摘要： In one embodiment, a semiconductor integrated circuit includes a first resistive-change element, a second resistive-change element and a first switching element. The first resistive-change element includes one end having a first polarity connected to a first power source. The first resistive-change element includes another end having a second polarity connected to an output node. The second resistive-change element includes one end having the second polarity connected to the output node. The first switching element includes a first terminal connected to another end of the second resistive-change element. The first switching element includes a second terminal connected to a second power source.
摘要翻译：在一个实施例中，半导体集成电路包括第一电阻变化元件，第二电阻变化元件和第一开关元件。第一电阻变化元件包括具有连接到第一电源的第一极性的一端。第一电阻变化元件包括具有连接到输出节点的第二极性的另一端。第二电阻变化元件包括具有连接到输出节点的第二极性的一端。第一开关元件包括连接到第二电阻变化元件的另一端的第一端子。第一开关元件包括连接到第二电源的第二端子。

6. 发明申请

US20120080737A1 SEMICONDUCTOR DEVICE PROVIDED WITH A NON-VOLATILE MEMORY UNIT AND A MEMS SWITCH 审中-公开
标题翻译：具有非易失性存储单元和MEMS开关的半导体器件
公开(公告)号：US20120080737A1
公开(公告)日：2012-04-05
申请号：US13051834
申请日：2011-03-18
申请人： Koichiro ZAITSU , Shinichi Yasuda , Shinobu Fujita
发明人： Koichiro ZAITSU , Shinichi Yasuda , Shinobu Fujita
IPC分类号： H01L29/788
CPC分类号： H01L27/11807 , H01L27/11521 , H01L27/11526
摘要： According to one embodiment, a semiconductor device is provided. The semiconductor is provided with a MEMS switch element having a control terminal and a pair of signal terminals, and a non-volatile memory unit having first and second non-volatile semiconductor elements. The first non-volatile semiconductor element has a first source, a first drain and a first control gate terminal. The first drain is electrically connected to the control terminal of the MEMS switch element. The second non-volatile semiconductor element has a second source, a second drain and a second control gate terminal. The second drain gate terminal is electrically connected to the control terminal of the MEMS switch element.
摘要翻译：根据一个实施例，提供一种半导体器件。半导体设置有具有控制端子和一对信号端子的MEMS开关元件，以及具有第一和第二非易失性半导体元件的非易失性存储器单元。第一非易失性半导体元件具有第一源极，第一漏极和第一控制栅极端子。第一漏极电连接到MEMS开关元件的控制端子。第二非易失性半导体元件具有第二源极，第二漏极和第二控制栅极端子。第二漏极端子电连接到MEMS开关元件的控制端子。

7. 发明授权

US07890560B2 Random number generating circuit, semiconductor integrated circuit, IC card and information terminal device 有权
标题翻译：随机数发生电路，半导体集成电路，IC卡和信息终端装置
公开(公告)号：US07890560B2
公开(公告)日：2011-02-15
申请号：US12122503
申请日：2008-05-16
申请人： Shinichi Yasuda , Shinobu Fujita
发明人： Shinichi Yasuda , Shinobu Fujita
IPC分类号： G06F1/02
CPC分类号： G06F7/58
摘要： A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.
摘要翻译：随机数产生电路接收以第一产生速率产生的第一数字随机数信号作为输出，产生第二数字随机数信号，该第二数字随机数信号的第二发生速率是第一发生速率的两倍。提供了包括随机数电路的半导体集成电路，IC卡和信息终端装置。

8. 发明授权

US07772035B2 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07772035B2
公开(公告)日：2010-08-10
申请号：US11860102
申请日：2007-09-24
申请人： Shinobu Fujita
发明人： Shinobu Fujita
IPC分类号： H01L21/00
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/31 , H01L25/50 , H01L2224/13099 , H01L2224/131 , H01L2224/9202 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01016 , H01L2924/0102 , H01L2924/01022 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01051 , H01L2924/01078 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A manufacturing method of a semiconductor device includes preparing a first semiconductor substrate having a first integrated circuit formed therein and including a plurality of first through substrate vias, and a second semiconductor substrate having a second integrated circuit formed therein and including a plurality of second through substrate vias, forming a solid-electrolytic layer on an upper surface of the first semiconductor substrate, mounting the second semiconductor substrate on the solid-electrolytic layer such that a lower surface of the second semiconductor substrate comes into contact with the solid-electrolytic layer, and applying a voltage between the plurality of first through substrate vias and the plurality of second through substrate vias, to form in the solid-electrolytic layer a plurality of connection electrodes, which are respectively connecting the plurality of second through substrate vias adjacent to the plurality of first through substrate vias to the plurality of first through substrate vias.
摘要翻译：半导体器件的制造方法包括：制备具有形成在其中的第一集成电路的第一半导体衬底，并且包括多个第一贯通衬底通孔;以及第二半导体衬底，其具有形成在其中的第二集成电路，并且包括多个第二穿透衬底通孔，在所述第一半导体衬底的上表面上形成固体电解质层，将所述第二半导体衬底安装在所述固体电解质层上，使得所述第二半导体衬底的下表面与所述固体电解质层接触;以及在所述多个第一至第二基板通孔和所述多个第二贯穿基板通孔之间施加电压，以在所述固体电解质层中形成多个连接电极，所述多个连接电极分别连接所述多个第二贯穿基板通孔首先通过基底通孔到达普拉首先通过衬底通孔。

9. 发明申请

US20100072614A1 3-DIMENSIONAL INTEGRATED CIRCUIT DESIGNING METHOD 失效
标题翻译：三维集成电路设计方法
公开(公告)号：US20100072614A1
公开(公告)日：2010-03-25
申请号：US12504272
申请日：2009-07-16
申请人： Shinobu Fujita
发明人： Shinobu Fujita
IPC分类号： H01L23/52 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A 3-dimensional integrated circuit designing method includes forming a temporary layout region for an original integrated circuit on an XY plane, the plane being short in an X direction and long in a Y direction perpendicular to the X direction, dividing the temporary layout region into 2N (N is an integral number of not smaller than 2) or more subregions in the Y direction, configuring one block for every successive N subregions to prepare a plurality of blocks, and forming N layers of layout by alternately folding each of the blocks in the Y direction in units of one subregion to selectively set a kN-th (k is an integral number not less than 1) subregion and (kN+1)th subregion of each block to one of an uppermost layer and lowermost layer.
摘要翻译：三维集成电路设计方法包括在XY平面上形成用于原始集成电路的临时布局区域，该平面在X方向上短并且在垂直于X方向的Y方向上长，将临时布局区域分成 2N（N是不小于2的整数）或更多个子区域，为每个连续的N个子区域配置一个块以准备多个块，并且通过交替地将每个块的每个块交替地折叠来形成N个层的布局以一个子区域为单位的Y方向，选择性地将各块的kN（k为1以上的整数）子区域和（kN + 1）个子区域设置为最上层和最下层中的一个。

10. 发明授权

US07653855B2 Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device 有权
标题翻译：随机数测试电路，随机数生成电路，半导体集成电路，IC卡和信息终端设备
公开(公告)号：US07653855B2
公开(公告)日：2010-01-26
申请号：US11875360
申请日：2007-10-19
申请人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
发明人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F7/58 , G01R31/3181
摘要： A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.
摘要翻译：随机数测试电路包括：计数单元，用于对随机数序列中的特定值比特的重复次数进行计数，串联发生的重复;检测单元，用于检测与随机数中的比特种类对应的多个数字数字序列，以及基于该数字确定随机数序列是否正常的确定单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式