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1. 发明授权

US08952548B2 Apparatus and method for increasing bandwidths of stacked dies 有权
公开(公告)号：US08952548B2
公开(公告)日：2015-02-10
申请号：US13077654
申请日：2011-03-31
申请人： Shyh-An Chi , Mark Shane Peng
发明人： Shyh-An Chi , Mark Shane Peng
IPC分类号： H01L23/48 , H01L25/065
CPC分类号： H01L23/48 , H01L25/0652 , H01L25/0657 , H01L2224/16145 , H01L2225/0652 , H01L2225/06548 , H01L2225/06572
摘要： A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies.

2. 发明授权

US09064715B2 Networking packages based on interposers 有权
标题翻译：基于插件的网络包
公开(公告)号：US09064715B2
公开(公告)日：2015-06-23
申请号：US12964503
申请日：2010-12-09
申请人： Yun-Han Lee , Mark Shane Peng , Shyh-An Chi
发明人： Yun-Han Lee , Mark Shane Peng , Shyh-An Chi
IPC分类号： H05K1/11 , H05K1/14 , H01L25/065 , H01L25/18 , H01L23/00 , H01L23/14 , H01L23/538
CPC分类号： H05K1/181 , H01L23/147 , H01L23/538 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2223/6677 , H01L2224/16225 , H01L2224/16235 , H01L2225/06565 , H01L2924/14 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1438 , H01L2924/15192 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H05K1/111 , H05K1/115 , H05K1/141 , H05K2201/10045 , H05K2201/10053 , H05K2201/10378 , H01L2924/00
摘要： A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.
摘要翻译：一种包装结构包括一个包括多个交换机/路由器的联网单元和耦合到该多个交换机/路由器的多个网络接口单元，以及包括多个金属连接的插件。内插器基本上没有内置的功能元件。功能元件在插入器之外并且结合到插入器上，其中功能元件通过多个金属连接电耦合到联网单元。

3. 发明申请

US20120250286A1 Apparatus and Method for Increasing Bandwidths of Stacked Dies 有权
标题翻译：用于增加堆叠模具带宽的装置和方法
公开(公告)号：US20120250286A1
公开(公告)日：2012-10-04
申请号：US13077654
申请日：2011-03-31
申请人： Shyh-An Chi , Mark Shane Peng
发明人： Shyh-An Chi , Mark Shane Peng
IPC分类号： H05K7/02
CPC分类号： H01L23/48 , H01L25/0652 , H01L25/0657 , H01L2224/16145 , H01L2225/0652 , H01L2225/06548 , H01L2225/06572
摘要： A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies.
摘要翻译：封装结构包括彼此相同的多个管芯托架。多个裸片载体中的每一个中的相应特征垂直地叠加在多个模具载体中的其它模具载体中的相应特征。多个管芯载体中的每一个都包括多个包括多个数据总线的穿通基板通路（TSV）。多个管芯载体通过多个TSV堆叠并彼此电连接。封装结构还包括多个器件管芯。多个器件管芯中的每一个被结合到多个管芯载体中的一个。多个数据总线中的每一个被配置为专用于多个器件管芯之一的数据传输。

4. 发明申请

US20120147567A1 Networking Packages Based on Interposers 有权
标题翻译：基于内插器的网络包
公开(公告)号：US20120147567A1
公开(公告)日：2012-06-14
申请号：US12964503
申请日：2010-12-09
申请人： Yun-Han Lee , Mark Shane Peng , Shyh-An Chi
发明人： Yun-Han Lee , Mark Shane Peng , Shyh-An Chi
IPC分类号： H05K7/00
CPC分类号： H05K1/181 , H01L23/147 , H01L23/538 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2223/6677 , H01L2224/16225 , H01L2224/16235 , H01L2225/06565 , H01L2924/14 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1438 , H01L2924/15192 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H05K1/111 , H05K1/115 , H05K1/141 , H05K2201/10045 , H05K2201/10053 , H05K2201/10378 , H01L2924/00
摘要： A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.
摘要翻译：一种包装结构包括一个包括多个交换机/路由器的联网单元和耦合到该多个交换机/路由器的多个网络接口单元，以及包括多个金属连接的插件。内插器基本上没有内置的功能元件。功能元件在插入器之外并且结合到插入器上，其中功能元件通过多个金属连接电耦合到联网单元。

5. 发明授权

US08716855B2 Integrated circuit system with distributed power supply comprising interposer and voltage regulator module 有权
标题翻译：具有分布式电源的集成电路系统，包括插入器和电压调节器模块
公开(公告)号：US08716855B2
公开(公告)日：2014-05-06
申请号：US12943395
申请日：2010-11-10
申请人： Shyh-An Chi , Mark Shane Peng , Yun-Han Lee
发明人： Shyh-An Chi , Mark Shane Peng , Yun-Han Lee
IPC分类号： H01L23/52
CPC分类号： H01L23/49811 , H01L23/481 , H01L23/49816 , H01L23/50 , H01L24/48 , H01L24/73 , H01L25/18 , H01L2224/06181 , H01L2224/13025 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads.
摘要翻译：一种具有插入器和具有第一和第二接合焊盘的集成电路的集成电路系统，所述集成电路管芯使用所述第一接合焊盘接合到所述插入器。具有在不同工作电压下操作的电路块的集成电路和与集成电路的第二接合焊盘键合的电压调节器模块。电压调节器模块将电源电压转换为相应电路块的工作电压，并通过第二接合焊盘将相应的工作电压提供给电路块。

6. 发明授权

US08276110B2 Reducing voltage drops in power networks using unused spaces in integrated circuits 有权
标题翻译：降低集成电路中未使用空间的电力网络中的电压降
公开(公告)号：US08276110B2
公开(公告)日：2012-09-25
申请号：US12692184
申请日：2010-01-22
申请人： Dinesh Baviskar , Wen-Hao Chen , Chung-Sheng Yuan , Mark Shane Peng , Yun-Han Lee
发明人： Dinesh Baviskar , Wen-Hao Chen , Chung-Sheng Yuan , Mark Shane Peng , Yun-Han Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78
摘要： A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.
摘要翻译：设计集成电路的方法包括提供包括电力网络的集成电路设计。提供一种电压降缓解系统，其包括被配置为在电力网络中自动找到源节点和终端节点的电力带增强器。添加了使用电压降缓解系统的用于电力网络的冗余带，其中冗余带将源节点和终端节点互连。在添加冗余带的步骤之后，可以添加虚拟图案。

7. 发明授权

US07565635B2 SiP (system in package) design systems and methods 有权
标题翻译： SiP（系统封装）设计系统和方法
公开(公告)号：US07565635B2
公开(公告)日：2009-07-21
申请号：US11697744
申请日：2007-04-09
申请人： Clinton Chao , Louis Liu , Lewis Chu , Mark Shane Peng , Chao-Shun Hsu , Kim Chen
发明人： Clinton Chao , Louis Liu , Lewis Chu , Mark Shane Peng , Chao-Shun Hsu , Kim Chen
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045 , G06F2217/40
摘要： SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system.
摘要翻译： SiP设计系统和方法。该系统包括系统分区模块，子系统集成模块，物理设计模块和分析模块。系统分区模块根据分区标准将目标系统划分为子系统分区。子系统集成模块根据子系统分区，至少一个SiP平台和IC几何数据生成目标系统的架构设计和/或成本估算。物理设计模块根据架构设计，子系统分区，SiP平台和IC几何数据，为目标系统生成具有物理路由的SiP物理设计。分析模块基于SiP物理设计和/或目标系统的模拟来执行子系统分区内的性能检查。

8. 发明申请

US20080233710A1 METHODS FOR FORMING SINGLE DIES WITH MULTI-LAYER INTERCONNECT STRUCTURES AND STRUCTURES FORMED THEREFROM 有权
标题翻译：用于形成多层互连结构和形成其结构的单模的方法
公开(公告)号：US20080233710A1
公开(公告)日：2008-09-25
申请号：US11689264
申请日：2007-03-21
申请人： Chao-Shun Hsu , Chen-Yao Tang , Clinton Chao , Mark Shane Peng
发明人： Chao-Shun Hsu , Chen-Yao Tang , Clinton Chao , Mark Shane Peng
IPC分类号： H01L21/30
CPC分类号： H01L25/0655 , H01L21/823475 , H01L23/481 , H01L23/522 , H01L2924/0002 , Y10T428/12229 , H01L2924/00
摘要： A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not include any active device The at least one fist metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die.
摘要翻译：用于形成单个管芯的方法包括在第一衬底上形成至少一个第一有源器件以及耦合到第一有源器件的至少一个第一金属层。在第二衬底上形成至少一个第二金属层，其中第二衬底不包括任何有源器件。至少一个第一金属层与至少一个第二金属层结合，使得第一衬底和第二衬底构成一个单一的死亡。

9. 发明授权

US09958895B2 Bandgap reference apparatus and methods 有权
公开(公告)号：US09958895B2
公开(公告)日：2018-05-01
申请号：US13004617
申请日：2011-01-11
申请人： Chih-Chia Chen , Mark Shane Peng
发明人： Chih-Chia Chen , Mark Shane Peng
IPC分类号： G05F1/10 , G05F3/02 , G05F3/30
CPC分类号： G05F3/30
摘要： Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals.

10. 发明申请

US20120176186A1 Bandgap Reference Apparatus and Methods 有权
标题翻译：带隙参考装置和方法
公开(公告)号：US20120176186A1
公开(公告)日：2012-07-12
申请号：US13004617
申请日：2011-01-11
申请人： Chih-Chia Chen , Mark Shane Peng
发明人： Chih-Chia Chen , Mark Shane Peng
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals.
摘要翻译：补偿带隙参考电路的结构和方法。具有非零温度系数的第一带隙基准电路的第一集成电路管芯; 并具有第一输出参考信号，第二集成电路管芯具有第二带隙基准电路，其具有与第一带隙基准电路的温度系数相反极性的非零温度系数，并具有第二输出参考电压提供信号; 设置在第一和第二集成电路管芯中的至少一个的加法器电路组合第一和第二输出参考信号，并输出组合的参考信号; 并且提供用于将第一和第二输出信号连接到加法器电路的连接器。公开了用于将集成电路管芯与带隙参考电路配对并耦合模具以形成温度补偿信号的方法。

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