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1. 发明授权

US10573636B2 ESD protection device and method for manufacturing the same 有权
公开(公告)号：US10573636B2
公开(公告)日：2020-02-25
申请号：US16372984
申请日：2019-04-02
申请人： Silergy Semiconductor Technology (Hangzhou) Ltd.
发明人： Fei Yao , Shijun Wang , Dengping Yin
IPC分类号： H01L27/02 , H01L29/861 , H01L29/06 , H01L29/66
摘要： Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.

2. 发明申请

US20180090477A1 TRANSIENT VOLTAGE SUPPRESSOR AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20180090477A1
公开(公告)日：2018-03-29
申请号：US15711146
申请日：2017-09-21
申请人： Silergy Semiconductor Technology (Hangzhou) Ltd.
发明人： Dengping Yin , Shijun Wang , Fei Yao
IPC分类号： H01L27/02 , H02H9/04 , H01L21/02
CPC分类号： H01L27/0248 , H01L21/02293 , H01L21/02697 , H01L27/0255 , H01L29/402 , H01L29/861 , H02H9/04
摘要： Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost.

3. 发明申请

US20170243965A1 BI-DIRECTIONAL PUNCH-THROUGH SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20170243965A1
公开(公告)日：2017-08-24
申请号：US15587518
申请日：2017-05-05
申请人： Silergy Semiconductor Technology (Hangzhou) LTD
发明人： Fei Yao , Shijun Wang , Bo Qin
IPC分类号： H01L29/74 , H01L29/747 , H01L29/66
CPC分类号： H01L29/7424 , H01L29/0649 , H01L29/6609 , H01L29/66386 , H01L29/747 , H01L29/861
摘要： In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor.

4. 发明申请

US20160300939A1 BI-DIRECTIONAL PUNCH-THROUGH SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：双向穿孔半导体器件及其制造方法
公开(公告)号：US20160300939A1
公开(公告)日：2016-10-13
申请号：US15088297
申请日：2016-04-01
申请人： Silergy Semiconductor Technology (Hangzhou) LTD
发明人： Fei Yao , Shijun Wang , Bo Qin
IPC分类号： H01L29/74 , H01L29/66 , H01L29/747
CPC分类号： H01L29/7424 , H01L29/0649 , H01L29/6609 , H01L29/66386 , H01L29/747 , H01L29/861
摘要： In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor.
摘要翻译：在一个实施例中，双向穿通半导体器件可以包括：第一导电类型的半导体衬底的第一区域中的第一晶体管，其中第一晶体管包括在半导体中的第二导电类型的半导体掩埋层衬底和半导体掩埋层上方的外延半导体层的第一外延区域，半导体掩埋层被配置为第一晶体管的基极; 以及与所述第一晶体管并联耦合的第二晶体管，其中所述第二晶体管处于所述第一导电类型的所述半导体衬底的第二区域中，其中所述第二晶体管包括所述半导体衬底上方的所述外延半导体层的第二外延区域，以及在所述第二外延区域中的所述第二导电类型的第一掺杂区域，所述第一掺杂区域被配置为所述第二晶体管的基极。

5. 发明授权

US10290624B2 ESD protection device and method for manufacturing the same 有权
公开(公告)号：US10290624B2
公开(公告)日：2019-05-14
申请号：US15730419
申请日：2017-10-11
申请人： Silergy Semiconductor Technology (Hangzhou) Ltd.
发明人： Fei Yao , Shijun Wang , Dengping Yin
IPC分类号： H01L27/02 , H01L29/66 , H01L29/861 , H01L29/06
摘要： Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.

6. 发明申请

US20170345811A1 METHOD FOR MANUFACTURING ESD PROTECTION DEVICE 有权
公开(公告)号：US20170345811A1
公开(公告)日：2017-11-30
申请号：US15606976
申请日：2017-05-26
申请人： Silergy Semiconductor Technology (Hangzhou) Ltd.
发明人： Dengping Yin , Shijun Wang , Fei Yao
IPC分类号： H01L27/02 , H01L29/41 , H01L23/62 , H02H9/04 , H01L23/60
CPC分类号： H01L27/0248 , H01L23/60 , H01L23/62 , H01L27/0259 , H01L29/41 , H02H9/04
摘要： Disclosed is a method for manufacturing an ESD protection device. The method comprises: forming a first buried layer on the semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a first doped region in the first epitaxial layer and forming a second doped region surrounding the first doped region in the first epitaxial layer, wherein the semiconductor substrate and the first doped region are both of a first doping type, the buried layer and the first epitaxial layer are both of a second doping type, the first doping type is opposite to the second doping type, the first doped region and the second doped region are formed using a same first mask. The method uses the same mask to form an emitter region of the open-base bipolar transistor, and to form a barrier doped region at the periphery of the emitter region, so that the manufacture cost is reduced and the parasitic capacitance of the ESD protection device is decreased.

7. 发明授权

US09679998B2 Bi-directional punch-through semiconductor device and manufacturing method thereof 有权
公开(公告)号：US09679998B2
公开(公告)日：2017-06-13
申请号：US15088297
申请日：2016-04-01
申请人： Silergy Semiconductor Technology (Hangzhou) LTD
发明人： Fei Yao , Shijun Wang , Bo Qin
IPC分类号： H01L29/747 , H01L29/74 , H01L29/66
CPC分类号： H01L29/7424 , H01L29/0649 , H01L29/6609 , H01L29/66386 , H01L29/747 , H01L29/861
摘要： In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor.

8. 发明授权

US11482519B2 Transient voltage suppressor and method for manufacturing the same 有权
公开(公告)号：US11482519B2
公开(公告)日：2022-10-25
申请号：US17193164
申请日：2021-03-05
申请人： Silergy Semiconductor Technology (Hangzhou) LTD
发明人： Dengping Yin , Shijun Wang , Fei Yao
IPC分类号： H01L27/00 , H01L27/02 , H01L29/861 , H01L21/02 , H02H9/04 , H01L29/40
摘要： Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost.

9. 发明授权

US10978441B2 Transient voltage suppressor and method for manufacturing the same 有权
公开(公告)号：US10978441B2
公开(公告)日：2021-04-13
申请号：US15711146
申请日：2017-09-21
申请人： Silergy Semiconductor Technology (Hangzhou) Ltd.
发明人： Dengping Yin , Shijun Wang , Fei Yao
IPC分类号： H01L27/00 , H01L27/02 , H01L29/861 , H01L21/02 , H02H9/04 , H01L29/40
摘要： Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost.

10. 发明申请

US20180047717A1 ESD PROTECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20180047717A1
公开(公告)日：2018-02-15
申请号：US15671816
申请日：2017-08-08
申请人： Silergy Semiconductor Technology (Hangzhou) Ltd.
发明人： Shijun Wang , Fei Yao , Dengping Yin
IPC分类号： H01L27/02 , H01L21/762 , H01L21/8222 , H01L21/761 , H01L27/06 , H01L29/06
CPC分类号： H01L27/0248 , H01L21/761 , H01L21/76224 , H01L21/8222 , H01L27/0259 , H01L27/0664 , H01L27/0761 , H01L29/0615 , H01L29/0649
摘要： Disclosed is a method for manufacturing an ESD protection device. The ESD protection device includes a rectifier diode and an open-base bipolar transistor, the anode of the rectifier diode is the first doped region and the cathode of the rectifier diode is the semiconductor substrate, the emitter region, base region and collector region of the open-base bipolar transistor are the second doped region, the epitaxial semiconductor layer and semiconductor substrate, respectively, the first doped region and the second doped region extend through the doped region into the epitaxial semiconductor layer by a predetermined depth. The doped region can suppress the induced doped region around the second doped region, so that the parasitic capacitance of the open-base bipolar transistor is reduced and the response speed is improved.

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